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The intrinsic conductivity is
governed by the band gap which determines the carrier density. The resistivity,
in turn, is given by carrier density times
mobility. It should thus be possible to give precise values. |
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However, upon closer inspection it turns out that
not only carrier mobilities are temperature dependent, but the band gap, and
the effective masses, too. That makes precise calculations difficult. We have,
e.g.
Eg(300 K)=1,1242 eV
Eg(0 K)=1,1700 eV.
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Measurements, while always possible, must allow
for non-perfection - there is no such thing as an perfect intrinsic
semiconductor. With lots of precautions, it is possible to grow crystals with a
resistivity (at room temperature) of about 1 000 Wcm - still far lower than the intrinsic value. |
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This should motivate a little
exercise: |
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As stated above, it is not easy to
produce Si with a conductivity close to the intrinsic limit. |
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Si wafers commercially available therefore
have resistivities r £ 100 Wcm (at room
temperature); if you want something better than that you have to negotiate with
the supplier. |
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An example for what is on the market can be
found in the link. |
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At the other end, large
conductivities, obtained by heavy doping, are limited by the maximum
solubility
of the dopants. The term "solubility" refers to the (temperature
dependent) equilibrium concentration of impurity atoms that can be incorporated
into a crystal as single atoms. |
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For concentrations higher than the
solubility limit, the surplus impurity
atoms would tend to precipitate - and precipitates of As, B, or
P, while possibly introducing defect levels in the band gap, are
not active as dopants. |
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The highest achievable meaningful doping levels
are thus given by the highest solubility of a doping element (always at a high
temperature) - provided it can be kept in solid
solution. This means that precipitation must be suppressed because
at room temperature the solubility is usually low. |
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The picture below shows solubility data for the
common Si dopants. In all cases the solubility is rather large (with a
maximum between 1200 oC and 1400 oC), and
may surpass the 1% level. |
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If the maximum concentration could be kept in solid solution while the crystal is
grown, the resistivity could be lower than
what has been listed above. However, this is neither feasible nor sensible.
Making devices always involves some heating, and if dopants are present in a
high supersaturation, precipitation may start during processing, leading to all
kinds of unwanted effects besides the unavoidable change in conductivity. |
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There is, however, no particular need
for high doping levels and a high precision
of doping. Making devices always means that local doping is optimized -e.g. while making a
source/drain area - and this requires medium to low doping levels of the
substrate which are easily achieved. |
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High doping is only important if the wafers are
used as substrate for epitaxial layers, and then the exact doping level is not
crucially important. |
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The real importance of the solubility
curves thus is in specifying how much doping can be achieved on top of the
initial doping by e.g. diffusion or ion-implantation. This will of course
depend on the temperature! |
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Ion implantation done at room temperature thus
always needs an annealing step to "activate" the dopants, i.e. to
dissolve them in the Si up to the solubility limit at the chosen
temperature. At the same time, this high temperature process also (hopefully)
"anneals" the lattice defects produced by ion implantation. |
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There are limits to
defect annealing, too: High doping
levels change the average lattice constant - especially the small B ion
reduces this parameter. Heavily B-doped layers thus want to contract,
and since this is not possible on top of a solid substrate, mechanical stress
is introduced which may lead to the formation of so-called "misfit
dislocations" -
the link
shows an example. |
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Silicon is an indirect semiconductor,
we expect
relatively large lifetimes and diffusion lengths. |
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This is indeed the case, lifetimes as large as
1 ms can be observed in extreme cases (This is an exceedingly long time
for an electron!) |
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The corresponding diffusion length approach
mm; again a very large distance for an atomic particle. |
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Some
numerical values linking
lifetime and diffusion length for Silicon can be found via the link |
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Lifetime and diffusion length are
direct measures of the cleanliness of Si with respect to "deep
level" impurities which act as life time killers as directly evident from
the Shockley-Read-Hall
theory. |
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There are many ways to measure the life time. A
particularly unconventional approach giving the most precise data for the
diffusion length is the "ELYMAT" technique, which is
discussed in an advanced module. |
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The ELYMAT and other tools like it have been used
extensively in the nineties to "clean up" Si production and
processing lines because even minute traces of contamination show up in a
reduced diffusion length. |
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While it is
generally important to maintain large diffusion lengths as a measure of
cleanliness (and for some electronic properties) in integrated circuits, it is
particularly important for solar cells. |
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Any carrier generated by light that recombines in
the bulk of the solar cell is lost for the external current that the solar cell
is supposed to produce. Diffusion lengths thus must be larger than the
absorption depth for solar light, otherwise the light generated carriers will
not be able to diffuse to the the surface junction and produce current. What
this means in practical (rather relaxed) terms is shown in the graph: |
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For CMOS grade Si the requirements
are much more stringent: Allowed levels of "life time killing" metals
are much lower and specified at < 5 · 1010
cm–3; i.e. at <1ppt (introducing now for the
first time the
ppqt - "parts per quatrillion" range).
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This is not so much because large lifetimes are
so important, but because the metals killing the lifetime time tend to
precipitate - and even extremely low densities (say 1 precipitate
/cm2) of extremely small precipitates (say 10 nm), if
contained in a critical part of a device - e.g. at the Si - gate oxide
interface - will kill a transistor and such the whole device.
An
example is given in the link. |
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Lattice defects in microelectronic
Si are easy to deal with: They are simply not
allowed! |
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While it is indeed possible to avoid
"larger" defects like grain boundaries, dislocations and sizeable
precipitates in Si crystals (cf. the relevant chapters of the "Electronic
Materials" and "Defects in Crystals" Hyperscripts),
there is no way to avoid point defects or small agglomerates of point defects,
also known as "BMD"s (bulk microdefects) or "COP"s (crystal originated particles or
pits), or
LLS (sometimes also
abbreviated LPDs):
Localized Light Scattering Defect.
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Why? Simply because point defects (vacancies and
self interstitials) will be present in thermal equilibrium during crystal
growth - and they cannot disappear at internal sinks like grain boundaries and
dislocations because there aren't any; and the surface as an external sink is
simply too far away for all but the surface-near point defects. The equilibrium
point defects thus will be either "frozen-in" during cooling or form
agglomerates which constitute the BMDs. |
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Usually, these microdefects are few and small -
it is not easy to detect them and often they are below the detection limits of
the most advanced methods. Historically, however, they are periodically
rediscovered because devices are becoming steadily smaller and more sensitive
and their (always negative) influence on device properties is felt at some
point. |
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As a curiosity, it shall be noted in
passing that point defect equilibria in Si are much more complicated
than in other elemental crystals and not very well understood up to this day.
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In particular, Si seems to be the only
elemental crystal so far where self-interstitials are present in thermal
equilibrium in concentrations that are comparable to vacancies (otherwise their
concentration is always much lower). This implies that both vacancies and
self-interstitials are involved in the formation of BMDs and that the
diffusion of substitutional impurities (including all dopants) might be more
complicated that usual. |
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Some more details can be found in the "Defects in
Crystals" Hyperscript. |
© H. Föll
