### Semiconductor International Nov. 2003

Wafer Bonding Enables New Technologies and Applications
Laura Peters, Senior Editor -- 11/1/2003
At a Glance
Whether the bonding process is activated by temperature, a plasma or chemicals, the technology of wafer bonding is unifying different materials to create new devices and microcomponents that cannot be fabricated using silicon alone. Wafer bonding is fueling the silicon-on-insulator (SOI) revolution, but MEMS and MOEMS are not too far behind.
Wafer bonding got its start in the manufacture of MEMS, mostly for automotive applications. Microsystems such as accelerometers, micromirrors and gyroscopes require a sealed microcavity to protect the device from harsh environments, while allowing the mechanical function to be performed. Other devices such as infrared (IR) detectors or resonant devices required a vacuum-sealed package. Later, wafer bonding was used for MOEMS, systems combining optical and electrical functions, with applications as varied as hearing aids and IR focal plane arrays. Beyond MEMS and MOEMS, three other applications drive wafer bonding technology: wafer-level packaging, 3-D chip stacking and silicon-on-insulator (SOI) wafers. The myriad of applications has led to several bonding methods (Fig. 1 ). Also, a new type of wafer bonding application is emerging that combines various materials as a means of designing novel devices. These custom-engineered substrates allow for combinations of materials that have been imagined for years, such as GaAs-on-silicon and InP-on-silicon for optoelectronic devices. Depending on the application, bonding requirements vary greatly. For MEMS, temperature and pressure uniformity across the wafer are essential, and wafers typically measure 75-150 mm. For SOI, neither high temperature nor force is applied. Instead, wafer cleanliness on the nanometer level is necessary, and 200 and 300 mm wafers must be accommodated. "The driving force for 300 mm was SOI on the one hand, and the other was 3-D interconnects," said Paul Lindner, chief technical officer at EV Group (EVG, Schärding, Austria). EVG recently introduced an alignment technology (Fig. 2 ) specifically for 3-D interconnect solutions, which require an alignment accuracy of <1 µm.
1. The choice of bonding method largely depends on the initial substrate, tolerance to temperature and the final application. (Source: SUSS MicroTec)
2. Rather than use a single microscope between wafers, the alignment technique for wafer-level 3-D interconnects uses a dual microscope to focus on a common axis calibrated for each alignment. Each objective observes one alignment key on the wafer surface. The two horizontal stages can be moved independently in 0.1 µm steps. (Source: EV Group)
SUSS MicroTec (Munich, Germany) and EVG are the largest suppliers of wafer bonders, from research tools to full production systems. In addition to the alignment/bonding systems, these companies also provide the ancillary equipment, including spin coaters and pre-cleaning modules, as well as in-line inspection tools. Bonding performance Wafer bonding is the only semiconductor processing tool that combines high temperature uniformity with high uniformity of force across the wafer. Because of the variety of applications, chamber pressure must be able to be rapidly pumped down to 10-5 mTorr or overpressure to the wafer as high as 3 bar might be applied. "For most bonding processes, temperature uniformity is essential — 1% uniformity across a 200 mm wafer," Lindner said. Such uniformity is achieved through specialized heating chucks with double-sided heating to control the temperature of wafers and the gradient across the stack, he added. For wafer-level packaging (WLP), bonding accuracy and uniformity are important, as well as the coplanarity of the bonded wafers. Substrate bonding also allows more flexibility in the process than the alternative, die-level flip-chip bonding, because the environment can be controlled to use nitrogen or forming gas or xenon, whereas flip-chip bonding is performed at room temperature and pressure. WLP of semiconductor devices or sensors also protects the devices from possible contamination of subsequent processes such as dicing. "I think wafer-level packaging will help the optoelectronic world because we are using standard resists and low-k materials in standard semiconductor processes like fusion bonding, so it's more friendly than a die-level flip-chip machine that required very high precision and used exotic packages like the butterfly package or the TO can, which the semiconductor industry wasn't used to working with," said Jeff Dumas, international product manager for wafer bonders at SUSS MicroTec. WLP typically uses adhesive bonding, one of many bonding methods. Bonding choices Wafer bonding can be used to join any two flat mirror-polished clean surfaces with various crystallographic orientations and lattice constants. Typically temperature, force and/or an intermediate layer are used to facilitate bonding. Silicon direct, anodic, eutectic and thermocompression bonding are common, while temporary bonding is increasingly being used with ultrathin wafers for smart cards. Anodic bonding joins a silicon wafer with a glass wafer that contains a high concentration of alkali metal oxides (often Pyrex). At elevated temperature (200-500°C), a high-voltage electric field is applied, which dissociates the oxides and drives the metal ions into the glass. The process creates an oxygen-rich layer at the silicon-glass interface. The electric field forces the oxygen ions to the silicon surface, resulting in a strong, irreversible bond. "In the case of silicon-to-glass, the anodic bond uses the conductive properties of the glass to create covalent bonds and a hermetic seal," Lindner explained. Anodic bonding is most used in WLP and sensor encapsulation. Eutectic bonds are used when a hermetic or vacuum seal is required, generally for sensors. It uses an intermediate bonding material that forms a eutectic alloy at a specific temperature, such as gold-silicon, gold-tin, or lead-silicon. The metal is usually deposited by plating, while the silicon source can be the wafer or CVD. Solid-liquid mixing occurs at temperatures slightly above the eutectic point and high contact force (40 kN). A hermetic solid seal forms upon cooling. Adhesive bonding uses photoresist, spin-on glasses or polymers to deposit a planarizing material between two wafers. Such materials can be annealed at low temperature to provide a low-stress wafer stack. Thermocompression bonding uses glass beads suspended in a carrier paste (glass frit) and deposited onto a substrate either in a blanket form or patterned using screen printing. After deposition, the solvents are removed by degassing, and then heat and pressure are applied to make a hermetic seal. Thermocompression bonding is used in hybrid circuit manufacturing, and is being explored by some companies for 3-D interconnect fabrication. Temporary bonding is typically accomplished using spin-on wax or dry adhesives to bond a wafer to a carrier face down while the backside is grinded and polished. Later, the wax is melted, or the polymer adhesive is exposed to UV radiation to automatically release the bond. Temporary bonding is needed for ultrathin devices used in smart cards and other portable applications. "In some cases, these thin substrates can be less than 100 µm thick, so they are very fragile and yield can be compromised if they are not handled appropriately," Lindner explained. Sapphire carriers are most commonly used because they can be machined to a very high thickness tolerance, he said. Silicon bonding Silicon direct bonding, also called fusion bonding, uses applied temperature and pressure to join two materials, often an oxidized silicon wafer (the device wafer) and a silicon donor wafer. Later, the top wafer is cleaved or planarized to form an SOI wafer. In high-performance microprocessors, the silicon device layer is typically 500 nm or thinner, whereas SOI sensor wafers typically have >2 µm silicon layers. SOI bonders are sold to companies such as Soitec (Bernin, France), Silicon Genesis Corp. (SiGen, San Jose) and Wacker Siltronic (Burghausen, Germany), the leading providers of SOI wafers to the semiconductor industry. A key drawback to fusion bonding is the high-temperature anneal required to activate the bond. Alternatively, companies are using plasma processing to reduce annealing temperatures from ~1000°C to 200-300°C. "The plasma alters the surface of the wafer, making it hydrophilic, typically," Dumas said. "Then it allows the wafers to become heterogeneous more readily with less temperature, so now we can perform fusion bonding on wafers at a reduced temperature." Silicon fusion bonding occurs in three steps: 1) cleaning and/or plasma treatment, leaving a hydrophilic surface with a specific contact angle; 2) particle removal combined with surface reactivation and bonding; and 3) a high-temperature anneal in a standard vertical furnace at anywhere between 200 and 1000°C. The bonding procedure is initiated when the wafers are brought into close proximity and pressure is exerted on the wafer edge, the prebond spreads across the bond interface under its own momentum (10-30 mm/sec) and fusion bonding occurs (Fig. 3 ). The process is completed in 2-6 seconds depending on wafer size and surface energy.
3. The three stages of bonding show wafers brought into close proximity with pressure on the wafer edge (left), the prebond spreads (middle), and the wafers are fused together (right). (Source: SUSS MicroTec)
In terms of volume, the greatest number of wafers bonded today is used in SOI applications. Applications are varied (Fig. 4 ), ranging from smart power devices, microwave components, optoelectronics and advanced analog ICs (all thick-SOI applications) to radiation-hardened ASICs and high-speed microprocessors (thin-SOI applications).
4. SOI was first used for its radiation-hardened aspect in military applications, but has branched into high-speed microprocessors, portable wireless, and sensors of various kinds. (Source: SUSS MicroTec)
Engineered substrates Engineered substrates refer to the combination of different wafers to form new materials. "What's really hot right now is the integration of heterogeneous thin-film materials such as indium phosphide on gallium arsenide or germanium to silicon," Dumas explained. One particularly interesting combination for optoelectronic applications is that of GaAs on germanium, due to the nearly perfect lattice match between the materials. Ziptronix Inc. (Morrisville, N.C.) offers bonded wafers using a technique that altogether avoids elevated temperatures. The company uses a series of chemical treatments, then removes the chemistry and puts the wafers in contact, whereupon they form covalent bonds between different materials. The first commercial offering is a lithium tantalate (LiTaO3) glass or quartz wafer that is used to make surface acoustic wave (SAW) filters for cell phones and other piezoelectric devices. The wet chemistry used in the bonding process is specific to the substrates, but the wafers must be completely dry before bonding can take place, noted Doug Milner, president and CEO of Ziptronix. "We get edge-to-edge wafer bonding, good yield and excellent quality due to the nature of the environment we perform the bonding in and the fact we use a simple chemical activation process." In the case of LiTaO3 and quartz, the lattice size is ~15% different, leading to high bond strength that can endure subsequent thermal and mechanical processing. Ziptronix is reportedly the only company able to attain high bond energies between wafers without using elevated temperatures. The company's commercialization of LiTaO3 on quartz wafers is the first of many engineered substrates to come. "The theory is that if you can mix and match materials, you can pick the best features of each, eliminate the undesirable features, and come up with a new class of materials and products that otherwise could not be built using either of the materials separately," Milner said. By combining ultrathin LiTaO3 on quartz, the company was able to make a piezoelectric material with a low coefficient of expansion (CTE), allowing use of lower-cost SAW filters in wireless networking applications that were previously dominated by the more expensive bulk acoustic resonance filters or bulky ceramic filters. "By keeping only a thin skin of lithium tantalate, which has a high CTE, we were able to produce a material capable of lower insertion loss, better out-of-band frequency rejection, and improved thermal stability for a higher-quality SAW filter," Milner said. In a similar sense, Milner points out that silicon and quartz have very different CTEs, so for large wafer sizes, a room-temperature bonding process is more attractive than fusion or anodic bonding methods. Aside from the cost savings, the bonded product has less residual stress than occurs with alternative bonding methods, and scalability to larger wafers is more straightforward, he said. Milner expects engineered substrates to play an important role in the power dissipation of high-speed devices in the future. "You can remove the silicon substrate from the back of the circuit, replace it with a very high thermally conductive material and solve thermal management problems that way," he said. Device stacking Three-dimensional stacking helps improve device packing density and signal delays without the associated yield hit that system-on-chip (SoC) devices suffer from. Key to accomplishing this high-accuracy process is wafer-to-wafer alignment without the use of backside alignment keys as are commonly used in other wafer bonding processes. According to Lindner, copper and polymer layers are the most commonly considered interface for 3-D interconnection. Since this process occurs once the interconnects on both chips have been fabricated, an ultraclean bond is required and only low temperatures and low contact forces can be tolerated. A key benefit of using a polymer, such as BCB (benzocyclobutane), as the intermediate layer is the low processing temperature (150-300°C) compared relative to most metal-to-metal bonds. Though interest in device stacking is very high, this wafer bonding application is still in the R&D stages. Conclusions Wafer bonding is a mainstream technology for MEMS and MOEMS fabrication as well as the fabrication of bonded SOI structures. High bonding alignment accuracy is a must for 3-D device stacking, an emerging market for wafer bonders. Because the requirements of SOI and 3-D interconnects are so different from those of sensor production, the equipment industry provides completely different platforms to meet the requirements.
For more information...
When you contact any of the following manufacturers directly, please let them know you read about them in Semiconductor International.
EV Group http://www.evgroup.com/ | SUSS MicroTec http://www.suss.de/ | Ziptronix http://www.ziptronix.com/