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45 nm Faces the Risks and Rewards of New Materials
Peter Singer, Editor-in-Chief -- 1/1/2005
At a Glance
Winning 45 nm technologies will have to be competitive, but also pragmatic and cost-effective. New materials have great promise, yet also pose significant risk.
Sidebars: Defining the 45 nm Logic Node
The semiconductor industry is now on a cycle where a new generation of technology is introduced roughly every two years. The 90 nm generation went into production toward the end of 2003, 65 nm is scheduled to go into production this year, and 45 nm technology is expected to go into production in late 2007 or sometime during 2008. These technology nodes, each designated by one of the smallest and most easily defined dimensions printed on the wafer — the minimum half-pitch of metal interconnects — is clearly spelled out in the International Technology Roadmap for Semiconductors (ITRS). However, the 2007-2008 timeframe for what people are calling "45 nm" is different than what you'll see in the ITRS, which doesn't show 45 nm going into production until 2010. For an explanation of this difference, see "Defining the 45 nm Logic Node ."
The latest version of the ITRS, released to the public just last month (http://public.itrs.net/), also indicates a shift from a two-year to a three-year cycle, but it's likely to be somewhere between the two and three years, experts say. In fact, as the industry diversifies, the concept of distinct technology nodes may go away altogether. "Many in the industry feel that the traditional, simple ITRS technology-node concept has outlived its usefulness," noted Texas Instruments' Bob Doering, who has been involved in roadmapping efforts from the beginning (1992). "One of the major goals in the 2005 ITRS is to provide a broader, more balanced perspective of the diverse drivers of semiconductor technology in the era of SoC/SiP and effective scaling." For now, however, all eyes are on the 45 nm generation. Although still years away from production, critical decisions with regard to what materials, process technologies and device structures will be used are being made now. "We're right at the point where 45 nm technology is transitioning from the research to the development phase," said Craig Sander, corporate vice president of technical development at AMD (Sunnyvale, Calif.). "Many of the decisions are already made for 45 nm. Others will occur during the development phase as we look at the details of what is really manufacturable and finish the development of the technology." Hans Stork, chief technology officer at Texas Instruments (Dallas), added, "We're in the middle of that time period where there's a tug going on between getting the decision in place and wanting to wait a little bit longer so we have less risk in the program. Six months from now, that window is probably closing. The design window, at least for the leading customers, is going in all earnest in 2005." Risks and rewards The benefits of scaling — simply making devices smaller — will still exist at the 45 nm node, in that it's possible to produce products with more transistors within a given cost and power window. To continue to make big gains in device performance, however, it will likely be necessary to turn to new materials and/or transistor architectures. "It's almost like looking at the periodic table and seeing no elements left behind," joked IBM's Clement Wann at the International Electron Devices Meeting (IEDM) last month. Among the new materials being considered for the 45 nm node are strained silicon, SiGe, high-k gate dielectrics (e.g., HfSiON), metal gates (fully silicided nickel, molybdenum), germanium on insulator (GOI), etc. The challenge, of course, is that there's a risk in going to any new material, since it may ultimately cause unforeseen yield or reliability problems. New types of transistor structures provide better control over leakage current while boosting switching speed and drive current. Extreme examples include 3-D structures, such as the finFET, or transistors with multiple gates, but less extreme examples that employ new materials, such as raised SiGe source/drains or embedded SiGe layers, are also contenders. New process techniques, such as flash annealing, are also likely to be required, as will immersion lithography. Improvements in chip performance cannot be limited, however, to what advances can be made in manufacturing. Better circuit design, power management, multiple threshold voltages and the use of body biases are all techniques that could be used to improve the power-performance tradeoff, Texas Instruments' Mark Rodder noted at an IEDM short course. Even simply making some critical interconnect wires shorter could help. Rodder sees companies as having three basic options at the 45 nm node, each with trade-offs: Keep the same architecture with scaled technology (e.g., with use of local strain as needed to overcome scaling limitations of conventional gate dielectrics). Keep the same architecture, with new materials (high-k dielectric instead of SiON, and/or metal gates instead of polysilicon gates). Switch to a new architecture and new materials (multiple-gate devices). For all options, improved power management and circuit design techniques will be implemented. Figure 1 compares present-day technology with these three options for high-performance applications, showing relative improvements in drive currents and a figure of merit, which is related to circuit delay.
1. Companies are faced with three options at the 45 nm node: Sticking with the same architecture (SA) and scaled technology (ST); SA with new materials (NM), or moving to both a new architecture (NA) and NM. For high-performance (HP) devices, new materials appear to be required. (Source: Texas Instruments, M. Rodder, S. Yu and R. Venugopal)
In the end, the key challenge is to meet product performance targets within power limits, with high yield and appropriate cost. The "choices represent a tremendous opportunity for success...or failure," Rodder noted. A good example of the first option was provided at IEDM in a joint paper by STMicroelectronics, Philips and Freescale, where the performance loss caused by a thicker oxide was offset by improvements provided by process-induced strained silicon.1 It's unlikely that companies will use the last option because of the high risk, although new structures are promising. Scaling limits In the past, performance gains were obtained through scaling: Gate lengths (and underlying channel lengths) were made smaller, gate dielectrics were made thinner and source/drain junction depths were made shallower, which was all aided by a continued reduction in power supply voltages and lower threshold voltages. The advantages of such scaling are now diminished because of complicated tradeoffs associated with power, short channel effects, reduced mobility, and the simple fact that dielectrics can't be made much thinner — traditional dielectrics are only about four atoms thick at the 65 nm node. Many, if not most, of the new developments that will be required for the 45 nm node are focused on improving the three key measures of transistor performance: low leakage current, high drive current and fast switching speed. Of course, the specifications for these vary depending on the application. High-performance devices need fast switching speed, for example, while minimal leakage current is the main goal for low-standby-power devices, such as those used in mobile phones. "We are seeing that conventional scaling is reaching some physical limitations. However, we are also finding that there are many ways that we can still enhance performance while maintaining low leakage levels in the transistor," Sander noted. "I think you're going to see pretty aggressive things still happening in transistor performance as we transition from 65 nm to 45 nm." Strained silicon Clearly, strained silicon will be included in those aggressive approaches. Seen as a process nuisance only a few years ago, the industry has strongly embraced strained silicon as a way to improve both electron mobility in NMOS transistors and hole mobility in PMOS. "Strain is something we're looking at and implementing even in 90 nm and extending that for 65 nm," Stork noted. "We'll probably optimize that yet again for 65 nm." Strain in silicon can be induced in several different ways: through stresses created by films and structures that surround the transistor, called process-induced strain, by embedding a silicon-germanium layer in the device under the channel, or through a "whole wafer" approach.2 Since the effects can be additive, it could well prove to be that process-induced and whole-wafer strain are complementary, so all types could be used. "The game is to figure out the trade-off between additional complexity, potential impact on yield and reliability against the performance benefit that they unquestionably have," Stork said. "It's an engineering effort that depends on a lot of details in the process integration." In general, tensile stress improves electron mobility and compressive stress improves hole mobility, so tensile stress is used for NMOS devices and compressive for PMOS. Sources of stress include a nitride film on top of the device, the oxide in the nearby shallow trench isolation structure, silicides and the interlayer dielectric. To improve PMOS device performance, people are also experimenting with SiGe raised source/drains that also induce strain in the channel. High-k/metal gates At the very top of the industry's wish list, if there were such thing, is a manufacturable high-k gate dielectric. It's seen as an absolute requirement for future device generations in order to reduce leakage currents.3 This is shown in Figures 2 and 3 . Unfortunately, despite years of work, an easy solution has not appeared.
2. For high-performance devices with conventional gate dielectrics, the drive current is less than what is specified in the ITRS at low supply voltages. This argues the case for high-k gate dielectric or metal-gate alternatives. (Source: Texas Instruments, M. Rodder)
3. Scaled SiON gate dielectrics with polysilicon gates do not meet 45 nm targets for gate leakage and effective oxide thickness in inversion (i.e., when the device is off). Scaled SiON may also have reliability problems, such as TDDB, NBTI and reduced mobility. (Source: Texas Instruments, M. Rodder)
"Progress had been good because it is a very complex and very demanding application, but it hasn't been good enough," Stork said. "From what is talked about in the conferences and the knowledge base that we think exists with all the experts, there's just not that clear kind of solution out there. At this point in time, with the level of uncertainty, that being ready in four years puts the odds against you." By far, the leading high-k candidate is a hafnium-based material, such as hafnium-silicate oxynitride (HfSiON). One of the problems with such a material is that it does not appear to be compatible with existing polysilicon gate materials, because of Fermi-level pinning.1 This makes the use of a metal gate mandatory. "You're then requiring a change in the gate dielectric and the gate material, so that's a double challenge, which is why it's difficult," Stork said. On the other hand, there may be advantages in going to a metal gate and not changing the gate dielectric used (Fig. 4 ). Work is underway to investigate the formation of gates with various types of metals with different work functions (NMOS and PMOS would require different work functions — p- and n-type — in bulk CMOS; the same could be used in fully depleted SOI devices). One way to achieve this is a FUSI (fully silicided) process where a conventional polysilicon gate is converted to a silicide, such as NiSi, and doped appropriately. Nitrogen-implanted molybdenum has been proposed as another option, as has an alloy of ruthenium and tantalum.
4. Metals gates can enable meeting 45 nm node targets for leakage currents. (Source: Texas Instruments, M. Rodder)
New structures As previously mentioned, 3-D or non-planar device architectures are emerging as candidates for the 45 nm node and below because of their improved current density, reduced short-channel effects and improved gate control. These go by many names, including tri-gate, finFET, omega-FET and, more generally, multigate FETs. In reality, these designs do not have distinctly separate gates, as they are still basically three-terminal devices, yet they do surround the gate on multiple sides to give better control. At IEDM, IMEC (Leuven, Belgium) announced multigate FETs implemented in SRAM cells that feature a tall fin of 70 nm, 40 nm higher than typically reported so far, resulting in an increased current density. The transistors have a physical gate length of 40 nm and 35 nm wide fins. Will tall and narrow fins be manufacturable at the 45 nm node or at even smaller dimensions? Good question. Bulk silicon vs. SOI One of the biggest debates in the industry today is over the need for SOI. Intel and Texas Instruments have publicly stated that they see no need for SOI, while others, such as IBM and AMD, which collaborate on technology development, say SOI is essential. "AMD made the move to silicon on insulator quite some time ago, at the 130 nm generation," Sander said. "We decided that it was something that was important for us to embrace for the advantages that we could get from it for performance and power that we've implemented in our Athlon 64 and Opteron family of processors. We plan to continue to use SOI technology at the 45 nm node." Sander said that he believes the industry will at some point move to a fully depleted transistor. "This structure leads to superior transistor characteristics that are needed for the future. SOI leads very naturally into fully depleted structures and is also probably the right substrate for most 3-D transistor implementations. It's also a unique substrate structure to do some inventive things such as the hybrid orientation transistors reported by IBM." Stork provided the alternative viewpoint: "The benefit of SOI as we continue to scale is becoming less. Why change track if we'll end up at the same point? We always favored the very low-cost implementation of the technology shrink, and SOI has not proven to be a lower-cost implementation." It's certain that the SOI debate will rage on, but it's also clear that it's one of those early decisions that have already been made for the 45 nm node.
References
F. Boeuf, et al., "A Conventional 45 nm CMOS Node Low-Cost Platform for General Purpose and Low Power Applications," IEDM 2004, p. 425. P. Singer, "Strain Equals Gain: The New Face of Silicon ," Semiconductor International, December 2004, p. 28. L. Peters, "The Manufacturing Outlook for High-k/Metal Gates ," Semiconductor International, November 2004, p. 17.
### Defining the 45 nm Logic Node Craig Sander, corporate vice president of technical development, AMD, Sunnyvale, Calif. Although the most recent International Technology Roadmap for Semiconductors (ITRS) does not show the 45 nm node going into production until 2010, each company will have its own set of design rules, and it is a vast simplification to expect that a node can be described by the small number of pitches and areas provided in the ITRS. Also, the ITRS has traditionally defined the node dates based on expectation for DRAMs — not logic. What you can expect for most logic ICs is that the 65 nm rule set (for each company) will provide a linear shrink relative to 90 nm of about 0.7, leading to a density increase of about 2×. (Take a block of logic implemented in transistors and interconnect and shrink it by a factor of 0.7 in each direction and the area will be about half of what it was in the previous generation.) This 0.7 linear shrink for each successive generation has characterized the logic IC industry for some time: 90/130=0.69, 65/90=0.72, and 45/65= 0.69. This is how the industry decided to pick "45 nm" rather than say "50 nm" as the name that is most typically used to describe the next node. I would define 45 nm technology as a technology that will shrink existing 65 nm design rules by a factor very close to 0.7. And yes, this does mean that one company's "45 nm" technology will be different from another's. However, at 45 nm, things could get a bit more interesting. It is possible, maybe even likely, that the companies that are first to introduce "45 nm" technology will actually ship products with a linear shrink factor that is greater than the traditional 0.7. This is because the industry is running into real limitations with the currently available lithography tools. The key to truly manufacturable "45 nm" technology will be high-NA (NA=1.2) 193 nm immersion scanners, and they are not going to be available as soon as the industry would like. Once they do become available, it will still take time to hone the processes that utilize the tools and to get these process implemented into high-volume manufacturing. Those that are first to introduce the next node might have to do so with less capable scanners and wind up shipping something more accurately referred to as "50 nm" or maybe "52 nm" technology.

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