Value-Added Wafers Push Chips Ahead
Aaron Hand, Managing Editor -- 11/1/2002 Semiconductor International
At a Glance
Although silicon-on-insulator (SOI) technology has been in the works for many years, leading chipmakers are finally embracing it for improved performance. Strained silicon is also beginning to offer complementary enhancements.
Low-k dielectrics, high-k dielectrics, copper — all significant and often-discussed materials issues in the quest for increased speed and performance. But if there is going to be any hope of continuing on the breakneck path called Moore's Law, there must be a change in the wafer substrate itself. As much as the industry has managed to scale transistors down, bulk silicon scaling simply cannot continue. Enter silicon-on-insulator (SOI) technology, strained silicon, and other substrate-enhancing effects. Or rather, enter their acceptance into mainstream chip production. The technologies have been around for several years. But the impending wall for the extension of bulk silicon capabilities, as well as improved manufacturing techniques for SOI and SiGe, have finally made chipmakers realize that they just can't live without them. SOI's day On SOI wafers, transistors are built on a thin layer of silicon, which sits on an insulator — commonly silicon dioxide. The isolation of the device's active domain lowers the parasitic capacitance, reducing the amount of leakage into the substrate and thereby enabling lower-voltage operation and faster operation.
Along with improvements in interconnects and dielectrics, chipmakers are looking to the wafer substrates themselves for better speeds and performance. Wafer upgrades include SOI and strained silicon. (Source: Soitec)
Though originally called silicon-on-sapphire (SOS) and somewhat less clever than it is today, the SOI concept has been around since the 1960s. In fact, IEEE has held an SOI conference annually for close to three decades. In the early days, the talk was mostly of SOI for space, aerospace and defense applications, the technology particularly suited to devices requiring resistance to radiation. Commercially, however, SOI is relatively new, and encompasses a wide array of applications, including microelectromechanical systems (MEMS), smart power, and high-speed microprocessors and memories (Fig. 1). SOI benefits include higher speeds, lower power consumption, low leakage current, the ability to withstand higher temperatures, and the integration of electrical and optical signals. Honeywell, which makes sensors and ICs largely for aerospace applications, had one of the first production-level chips to market, and now bases all of its product technology on SOI, according to Gary Kirchner of Honeywell's Solid State Electronics Center (Plymouth, Minn.). In addition to space applications, Honeywell is beginning to use SOI for wireless applications and MEMS pressure sensors. SOI enables the sensors to withstand higher temperatures — up to ~200°C — important for the automotive market.
1. SOI is relevant to a wide range of applications, each taking advantage of a different thickness of the silicon layer. (Source: SiGen)
IBM has also long been a proponent of SOI, announcing some four years ago its implementation of SOI for mainstream use. Immediately, the company saw a 25% gain in the speed of its chips. The 180 nm node was implemented in both bulk silicon and SOI, according to Ghavam Shahidi, IBM Fellow and director of high-performance logic devices at IBM's Microelectronics Division (Hopewell Junction, N.Y.). At the 130 nm node and beyond, IBM will use only SOI for its high-performance CMOS technology. Motorola and AMD are two more big supporters, both making progress in thin-film SOI integration. System-on-a-chip (SoC) is one application that demands customized wafer substrates, noted Marius Orlowski of Motorola's Semiconductor Products Sector (Austin, Texas). Although Intel had previously insisted that it was in no hurry to add SOI to its process because its bulk CMOS could handle continued scaling, even it has lumbered over to SOI. The microprocessor giant announced about a year ago that, along with structural enhancements to its transistors, it would be introducing SOI into its process. However, it does not plan to introduce the technology as early as other players. "Bulk silicon scaling has ended," IBM's Shahidi said. The industry will be looking more and more at SOI, strained silicon, silicon germanium — or any combination of these materials enhancements — as semiconductors move beyond the 90 nm node, he said. "Bulk scaling is becoming challenging at 90 nm. Simple bulk scaling at the 65 nm node is extremely challenged, due to limitations in oxide scaling and high doping levels needed to control the short channel effect." Philips Semiconductors, which began exploring SOI in the 1980s, uses thick-film (1.5 µm) SOI for power ICs, with applications in audio, automotive, display, power-conversion and lighting applications, according to René P. Zingg, manager of HV-SOI process development at Philips (Nijmegen, Netherlands). More than 70 million SOI-based chips have been shipped to customers, he noted, primarily in automotive applications. "The SOI share in our power-IC fab has been in excess of 10% for more than a year," he said, adding that Philips also has SOI R&D activities in rf and other fields. Besides area reduction, improved robustness and switching speed, electromagnetic compatibility (EMC) performance — a unique selling factor in automotive and Class-D audio applications — is a factor of 10 better in SOI than it is with bulk technology, Zingg said. Mitsubishi Electric is exploring SOI for the advantages it offers its high-speed Ethernet transceivers, according to Tadashi Nishimura of Mitsubishi's ULSI Development Center (Hyogo, Japan). Besides the benefits of lower power consumption and lower voltage, SOI enables the integration of multiplexer/demultiplexer and logic circuits, he noted. "A few years ago, production people were scared to put SOI in their fab lines," said Andrew Wittkower, president of Soitec USA (Peabody, Mass.). "That no longer exists; people are very, very comfortable that it will not contaminate, not cause any problems." How it's done Two main technical approaches compete in SOI: oxygen implantation and wafer bonding. The leading implant method is separation by implantation of oxygen (SIMOX), whose leading manufacturer is Ibis Technology (Danvers, Mass.). SIMOX bombards a wafer, implanting it with high-energy oxygen ions. Annealing at a very high temperature turns it into SiO2, creating the buried oxide layer. This technique uses a special implant tool because it requires wafers to be implanted at a high temperature (>400°C) and doses some 100× higher than typical semiconductor ion implanters. Wafer bonding techniques bond a seed wafer with a thermally grown SiO2 layer to another wafer, sandwiching the oxygen layer between the two substrates. A portion of the seed wafer is removed, leaving a thin layer of silicon next to the oxide. Several companies are involved in the wafer bonding process, including Soitec (Bernin, France), Silicon Genesis (SiGen, San Jose), Canon (Hiratsuka, Japan), and Isonics (Golden, Colo.). The processes have similarities, but they differ in several respects. Although some companies are still involved in BE (bond and etch) or BG (bond and grind) processes, a few manufacturers remove the unwanted portion of the seed wafer in such a way as to recycle it as the new seed wafer. Soitec, which claims ~80% of the thin-film SOI market, began producing SOI wafers in 1992 with the SIMOX method. By 1996, however, the company had switched to a wafer bonding process called Smart-Cut to produce its Unibond wafers. Before bonding the oxidized wafer to the handle wafer, this technique implants the wafer with hydrogen, which is later activated to split the remainder of the seed wafer from the SOI wafer. After splitting, Soitec anneals the wafer and performs chemical mechanical polishing (CMP) to smooth the surface. SiGen is a relatively new company to the field. Although its process flow is similar, SiGen's SOI process differs with respect to the cleaving technique (it uses gas pressure to force the wafers apart at room temperature), the bonding technique, and the avoidance of CMP. Unlike Soitec's wet chemical bonding process, SiGen bonds the wafers by exposing them to a low-power plasma, which creates a system of dangling bonds, explained Michael I. Current, director of technology marketing for SiGen. The wafers bond almost instantly, he said, getting very quickly to a 75% covalent bond strength. Not only does this enable bonding at room temperature, he added, it has a positive impact on yield because of a decrease in bond voids. Because it avoids post-split polishing, SiGen is able to achieve thinner, more uniform silicon films, Current contends. It has achieved films as thin as 15 nm, compared with the 50 nm that Soitec reports. "With our technique, after we split the wafer, we don't touch it," Current said, explaining that they put it back in the epitaxial reactor, where silicon is removed on an atomic level by chemical vapor etch. "You can thin just as uniformly as you can make a film grow." For its ELTRAN (epitaxial layer transfer) method, Canon also avoids post-split polishing of the wafers, completing the final surface finishing with H2 annealing. Its splitting process uses a water-jet technique that enables the recycling of the seed wafer. Each SOI method has its advantages and disadvantages, so chipmakers often use a variety of wafers. "The different SOI technologies offer different ranges and accuracies for SOI film as well as buried layers," Zingg said, noting that Philips researchers have evaluated Unibond, SIMOX, BE-SOI and ELTRAN wafers and selected an economic solution for each of their processes. Thin- vs. thick-film SOI Whatever the method, SOI wafer manufacturers have made progress in recent years on how thin and how uniform they are able to make their wafers. High-speed microprocessor and memory manufacturers are certainly interested in thinner SOI, but not all customers feel the same. High-power ICs such as those made by Philips require thick-film (>1 µm) SOI, the higher voltages requiring a thicker oxide layer. A very rapidly growing field, SiGen's Current noted, is in infrared optics, where manufacturers of optoelectronic components such as silicon waveguides are interested in processing 1.5 µm wavelengths. "They use an SOI wafer that's maybe 5 µm thick," he said.
2. Compared with bulk CMOS, SOI offers better control over short channel effects, particularly as the films thin. (Source: IBM)
Nonetheless, thin films is where the cutting edge is, and it's where the market growth is expected. The industry has begun to talk of ultrathin SOI, with films <50 nm thick. "From the electronics point of view, that's the growth area," Current said. As films get thinner, manufacturers see much better control over short channel effects. Taking the silicon all the way down to 25 nm thick creates devices with extremely constant threshold voltages across varying channel lengths (Fig. 2). "Two years ago, our biggest product had 2000 Å of silicon. Now it's somewhat more than 1000 Å. In a year or so, it'll be 500 Å or less," Wittkower said, explaining that thinner silicon layers creates greater challenges for the SOI wafer manufacturers. "If you keep the same absolute value of uniformity, it isn't good enough; you have to make it more and more uniform." And, as silicon layers get thinner, the move is on from partially depleted to fully depleted SOI. "Everybody and their cousin is working on fully depleted SOI," Current said. Most of the partially depleted devices these days have a silicon layer of ~100 nm, he said. At about 50 nm, there may be some partially depleted and some fully depleted devices, but beyond that, they're likely to be fully depleted. In partially depleted SOI, there's a floating body effect in the undepleted region below the silicon device layer. For some applications, that floating body could come in handy. For example, it can store a charge, which could be used to increase the speed of the device because it temporarily lowers the threshold voltage. Toshiba has in R&D a technique for using partially depleted SOI as a replacement for on-chip DRAM, according to Current. "It doesn't give you the same retention time, but it's quite adequate for system-on-a-chip," he said, adding that it's one quarter or less the size of a traditional DRAM cell. Despite the ongoing potential of partially depleted SOI, fully depleted SOI, with its smaller gate size, is "a designer's delight," Current said. "That's the ideal transistor function because it has very, very sharp turn-on characteristics." But the fully depleted mode requires much thinner films, and processing requirements are very tight, Current noted. Manufacturers have been working over the past year or so to get a better handle on thickness control. Because fully depleted SOI fills up the entire device layer thickness, the threshold voltage will vary if the thickness varies at all, Current explained. "That's why, all around, we've improved our performance by almost an order of magnitude of last year." Increased infrastructure needed Although technical challenges still exist, much concern today is over the industry's ability to produce enough wafers. "The big challenge for the whole industry is the scale up of manufacturing," Current said. Even pessimistic forecasts predict that the market will reach millions of wafers a year within two to three years. "It's hard to imagine where that's coming from." Soitec recently opened its second SOI wafer fab, Bernin II, which will be devoted to 300 mm production. "Since we use standard equipment, we don't have to worry about 300 mm equipment availability," said André-Jacque Auberton-Hervé, president of Soitec. Soitec points to this factor as the key to manufacturability of the wafer bonding method, contending that SIMOX's need for home-grown equipment does not afford it the ability to go to high volumes of wafers very easily. At full capacity, Bernin II will be able to produce 2 million wafers per year in 200 mm equivalents. Bernin I, which hit full capacity this year at 800,000 wafer starts per year, has eight 200 mm production lines and one 300 mm line. Overall, the players have little capital to invest in this area, Current said. IBM still makes some of its own SOI wafers, he said, because the company cannot get enough wafers of sufficient quality from the wafer suppliers. "That's just the tip of the thing. Once AMD and Motorola ramp up, and once Intel rolls in two to three years, we're talking about a quarter million wafers a month. That requires a huge infrastructure." But the industry has no choice but to make it happen, Current said. They simply cannot make bulk circuits with a low enough off current. As they increase the number of transistors on a chip, and each transistor continues to leak, that would put the chips beyond the regime where they can support a battery, ruling out the possibility of chips for portable devices. Strained silicon, SiGe Chipmakers are also looking to strained silicon and SiGe as a material means of improving transistor speed and performance. Strained silicon works by taking advantage of the ~4% lattice difference between silicon and germanium. A layer of silicon is grown on top of SiGe. The atoms in the silicon layer align with those in the SiGe layer, stretching slightly to match the larger SiGe lattice. The increased spacing improves the mobility of the electrons (see "Strained Silicon Ready for Prime Time"). Researchers at IBM last year announced the fabrication of strained silicon devices that were up to 35% faster than their bulk CMOS counterparts (see Semiconductor International, July 2001). Although there have been many breakthroughs in this area, there are still challenges to overcome, Shahidi said. "We are confident we will use strained silicon on oxide in our 65 nm, because that is one of the very few methods of enhancing the performance." Intel recently unveiled a 90 nm process that combines strained silicon with copper interconnects and low-k dielectrics (see Semiconductor International, September 2002). According to researchers at AmberWave Systems (Salem, N.H.), a new company licensing strained silicon technology, the concept may also work well for growing GaAs on SiGe. Most players see SOI and strained silicon as complementary rather than competing technologies, which means that it's likely for strained silicon to become yet another offering for those manufacturers already selling SOI wafers. SiGen has been working with SiGe, for example. Published data suggest that one can achieve a factor of 2 improvement in carrier mobility, according to Current. Continued increases in the amount of germanium can bring even higher mobilities. Soitec also plans to be a SiGe supplier. "Strained silicon is in the R&D stages now," Auberton-Hervé said. "If it goes to market, it will be a product for Soitec."
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