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Strain Equals Gain: The New Face of Silicon
Peter Singer, Editor-in-Chief -- 12/1/2004
In an era where the benefits of simply making devices smaller and smaller are diminishing, new materials innovations that can improve device performance are key. One such innovation that provides dramatic improvements — a 75% increase in carrier mobility in some cases — with relatively little added complexity or cost is strained silicon.
Strain in silicon can be induced in two different ways: through stresses created by films and structures that surround the transistor, called process-induced strain; or by employing a strained silicon wafer, where the top layer of silicon has typically been grown on top of a crystalline lattice that is larger than that of silicon, typically silicon with 20% or more germanium content. The top layer of silicon stretches to conform to the larger lattice, which induces stress. With a process developed by Soitec (Bernin, France), it's possible to cleave off the top layer of strained silicon and bond it to a donor substrate, eliminating the germanium from the process. Soitec has been sampling 200 mm strained SOI since 2003, and recently announced 300 mm strained SOI (sSOI) capabilities. Wafer-level uniaxial strain can also be achieved, as announced recently by SiGen (San Jose). Through an interesting twist of nature, process-induced strain — which exerts strain uniaxially — gives the biggest boost to PMOS device performance. Whole-wafer strain, which is biaxial, has the biggest impact on NMOS device performance. Most leading-edge companies employ process-induced stress in some form in production today (typically tensile nitrides to improve NMOS device performance), but even greater benefits appear possible. Whole-wafer biaxial strain is a newer technology and still in a developmental phase, but it could well prove to be that process-induced and whole-wafer strain are complementary, and IC manufacturers may eventually use both to fine-tune the strain. Process-induced strain Some of the latest developments in process-induced strain will be presented this month at the International Electron Devices Meeting (IEDM) in San Francisco. "With strained silicon, we will continue having Moore's Law on track for 90 nm, 65 nm, 45 nm and beyond," noted Reza Arghavani, senior director in the thin films product group at Applied Materials (Santa Clara, Calif.), which will be presenting at IEDM and also hosting a panel session on strained silicon. In general, tensile stress improves electron mobility and compressive stress improves hole mobility, so tensile stress is used for NMOS devices and compressive for PMOS. Sources of stress include a nitride film on top of the device, the oxide in the nearby shallow trench isolation structure, silicides and the interlayer dielectric. The challenge is to understand and optimize how the stresses from these various films interact: "We expect that a lot of the different sources of process-induced stress can be additive, such as compressive nitrides for CMOS. We're looking at simulations of the various sources of process-induced stress to see how they can be optimized," said Faran Nouri, distinguished member of the technical staff for the front-end products group at Applied Materials. Arghavani added, "We've made significant innovations in certain areas of the process that would actually enable process-induced stress even further. For example, in the area of nitride, we are actually able to create a nitride with stress that can vary from 2.5 GPa compressive to 1.5 GPa tensile at 400°C. If you go to higher temperatures, we can even do better." To improve PMOS device performance, people are also experimenting with a layer of silicon germanium (SiGe) topped with strained silicon. "SiGe specifically induces a very large unaxial strain in the channel — it's much larger than you would get from the biaxial strained silicon that silicon manufacturers provide. We're able to introduce very, very large unaxial stress in the channel of the PMOS device," Nouri said. Results with SiGe to date are impressive: a 75% improvement in carrier mobility and a 35% improvement in Idsat. This approach, however, leaves germanium near the device, and there is some concern that it could up-diffuse into the channel or otherwise contaminate the device. It also creates new challenges in etch. Proponents point out that SiGe has been in production for years, since the mid-1990s, for HBT devices, and that problems with up-diffusion can be avoided by carefully controlling the thermal budget. Germanium-free whole-wafer strain
Macro-raman map of a quarter of a 300 mm sSOI wafer. Mean value 1.5 GPa, max-min <0.1 GPa. (Source: Soitec)
"Whole-wafer" strain is a technology being developed by wafer suppliers. The latest development in this area is a strained SOI layer, where strained silicon is grown on a SiGe substrate, oxidized, cleaved and bonded upside down onto a donor substrate (Figure ). The oxide then becomes the buried SOI layer. The advantage of this approach is that there is no germanium in the final product. Carlos Mazuré, Soitec's chief technology officer, talked about potential problems with germanium: "Arsenic diffuses very fast in silicon germanium, so it's necessary to remodel the p-n junction formation. Germanium will out-diffuse if you have a thermal budget that is too high. Germanium will up-diffuse into the strained silicon, changing the character of the silicon, so it will affect the mobility and enhancement factor. Or even worse, germanium could diffuse all the way up to the surface, leading to early failure of your gate oxide." Mazuré added that some customers were concerned with germanium contamination in furnaces and cleaning baths. "Germanium-free is much more compatible with the standard silicon processing infrastructure," he said. For additional information on wafer processing, go to www.semiconductor.net/wafer

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