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Power: The Primary Scaling Constraint?
Peter Singer, Editor-in-Chief -- 10/1/2002 Semiconductor International
The semiconductor industry is obsessed with device scaling limits. Assuming the industry can come up with ways to cost-effectively produce ever smaller devices, the main question is, When will physical scaling limits be reached? So far, these physical limits have been thought of mostly in terms of transistor behavior (i.e. short-channel effects and tunneling leakage) and time delays in the wiring. But, according to new research out of IBM's Semiconductor Research and Development Center (SRDC, Yorktown Heights, N.Y.), an important limiter has been largely ignored: power. According to David Frank, who is scheduled to present new findings at the International Electron Devices Meeting (IEDM) later this year, power should be taken as the primary constraint that determines how far technology can scale, and the different power constraints associated with different applications result in different limits to scaling. Because dimensional scaling has proceeded faster than voltage scaling, circuits are now so dense that power dissipation is a serious problem, he said. It is becoming necessary to design devices specifically to satisfy system power constraints, in addition to being faster, smaller and cheaper. Considering power as the final scaling limit leads to the conclusion that the final stage of scaling is optimization, Frank said. In short, everything about the design (gate length, oxide thickness, threshold voltage, supply voltage, wiring density, etc.) should be optimized to maximize the performance of a given application within its power constraints. Frank has carried out these optimizations, and will report them for the first time at IEDM, to be held Dec. 8-11 in San Francisco. Frank used two simplified models to capture the overall behavior of the system optimizations. In the first approach, the total logic transition rate (LTR) — defined as the total number of transitions per second — of the system is maximized while subject to a fixed total power dissipation. In the second approach, a new optimization variable is maximized. This variable is the return on investment (ROI), equal to LTR × tLife/(area × cost/area + power × cost/W), where tLife is the lifetime of the product, and cost/W is also over the lifetime of the product. In this way, says Frank, performance, area and power are all merged into one relevant variable. Furthermore, the ratio of cost/area over cost/W yields a purely economic power density parameter Pecon that can be used to characterize different applications.
1. Device and technology optimization results, comparing method. Solid lines and open symbols are for maximizing LTR subject to fixed power constraints. Dashed lines and solid symbols are for maximizing ROI. (Source: IBM)
Figure 1 shows optimized MOSFET dimensions based on the maximum ROI. The optimizations assume idealized super-halo extreme retrograde-doped bulk MOSFETs in which the threshold voltage and the depletion depth can be independently controlled. An oxynitride gate insulator is assumed as well as k=2.5 wiring dielectric.
2. Change in optimized performance for various technology alterations for the ROI model. Comparisons are relative to the base case. Note: low k means wiring permittivity k=1.5 (2.5 in base case); “low pwr” means circuit techniques are used to turn off two-thirds of the inactive devices, eliminating their leakage; “high mu” means that the mobility is increased 1.5× relative to the base case; “low temp” means that the junction temperature is 0°C, rather than 65°C, for purposes of calculating kT. Comparisons assume that the change in volume manufacturing cost due to the technology alterations is negligible. (Source: IBM)
Frank said the most important conclusion of his optimizations is that the scaling limits are very robust, remaining essentially the same for both the engineering and economic approach. The optimization procedures can also be used to evaluate other scaling issues. Figure 2 shows the impact of various technology changes on the maximized ROI for full technology optimization. By accumulating many such one-time changes, the industry can hope to continue increasing the performance of computational electronics, Frank said. For additional information on wafer processing, go to www.semiconductor.net/wafer.

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