High-k Materials Challenge Deposition, Etch and Metrology
Alexander E. Braun, Senior Editor -- 11/1/2002 Semiconductor International
At a Glance
Increasingly smaller and higher-performance devices are spurring the search for new high-k materials. Hafnium oxide and zirconium oxide are only two of those being considered. Further advances are being pursued in deposition, etch and metrology technologies as well.
The semiconductor industry is feverishly ferreting after a high-k material with a low equivalent oxide thickness (EOT) that provides, very thinly, silicon dioxide's dielectric properties, minus the leakage. The search is spurred by the urgency to rein in power consumption, particularly for battery-driven high-performance devices such as advanced memories. So far, however, promising high-k materials also bring electrical disadvantages and processing difficulties, and so the quest continues (Fig. 1).
1. Innovative ways to integrate high-k into advanced gate structures are being developed. Shown is a TEM cross section of a 50 nm gate structure integrated with high-k material as the gate dielectric. A 193 nm photoresist was used in combination with an advanced patterning film, a carbon hard-mask film, and etch integration scheme with resist trim. The patterning film is an amorphous carbon layer with a thin SiON cap layer, and was used as a mask to etch the poly gate and, subsequently, for selective removal of the high-k material. After etch, the patterning film was stripped in situ. The operation is done in an integrated concept minimizing process steps. (Source: Applied Materials)
Paul Meissner, vice president and general manager, Thermal Systems and Modules Transistor Group, at Applied Materials (Santa Clara, Calif.), does not see a final material choice any time soon. "Until you stop calling it 'high-k' and start calling it by a name, whatever it may be, the industry won't have made a decision on which gate dielectric to integrate. While there's no decision yet, there's strong momentum toward HfO2-based materials." "Manufacturers are running oxynitride in production," said Scott Becker, vice president of product management, Surface Conditioning Division, at FSI International (Chaska, Minn.). "They need a higher-k material, and there are too many roadblocks to using unary oxides — a pure HfO2, a pure ZrO2 — for them to be implemented soon." "The time for high-k has arrived," said Werner Rust, vice president of sales and marketing for Genus (Sunnyvale, Calif.). "We're working with customers using leading-edge technology as it pertains to material choices, and have ALD tools for many of these. We started out broadly with dielectrics, metals and combinations, and it's boiled down to a sharp focus on dielectrics for memories." The deposition question Meissner sees atomic layer deposition (ALD) as one more technique considered for high-k materials. "There are flash memory high-k applications, and early R&D being done to use materials such as HfO2 or aluminate structures. Capacitors are getting larger and high-k materials are counted on to reduce die area. In the gate area there's no deposition technique consensus, although there is agreement about the material itself, something HfO2-based." HfO2 has been successfully deposited using ALD, metal organic chemical vapor deposition (MOCVD), and physical vapor deposition (PVD). "This may not be the ultimate solution because there are concerns about a sputtering plasma in gate oxide's proximity," Meissner said. Applied currently offers the MOCVD approach because it expects that one of the most likely insertion points for high-k will be for slightly thicker EOTs, but low leakage requirements — as in extremely low-power parts — not necessarily for scaling. "MOCVD-based solutions satisfy low-leakage mobile application requirements," Meissner explained. "It's simpler to control film stoichiometry with MOCVD than ALD. This is a factor in high-k material creation because you get thermal stability, mobility, most of the integration issues — boron penetration through the gate — which are determined by gate stoichiometry rather than the dielectric itself." Additionally, precursors limit ALD. Currently, there is no precursor to form a hafnium silicate — just HfO2 films. Depending on integration, HfO2s crystallize at fairly low temperatures, and catastrophic defect formation may result. Techniques are being investigated for multilayer films, but none has proven satisfactory. With MOCVD, silicate formation is straightforward — it just uses hafnium, oxygen and silicon together. This provides higher thermal stability, retains stoichiometry at higher temperatures, and resists recrystallization. "We're also developing ALD of the scaling of the equivalent oxide thickness targets needed for microprocessor applications," Meissner said. "Hybrid films may be used, so supporting ALD is a must. It's promising for advanced memory films and flash films where constraints are more relaxed, and stoichiometry issues — particularly for capacitor applications — and thermal budget requirements are less severe." Challenges remain for the gate oxide. The most troubling one — particularly with high-performance logic — is mobility degradation. Stoichiometry control tunes mobility. Advanced memory's problems differ because of thermal budgets. "The materials are different. Ta2O5 was a choice but is almost abandoned. Some still consider it, but the move is to simpler materials. Ta2O5 won't be the material of choice for generations," Meissner said. Others are simpler to integrate and, although lacking Ta2O5's high k value, simpler ALD deposition makes up for it. "Capacitance enhancement is gained through good step coverage around the hemispherical grains used for the base," he said. "If the HSG areal enhancement is increased to where ALD must be used, then it's more important to have a good step coverage film instead of the highest possible dielectric constant, because gaps or voids degrade capacitance." From the channel substrate there are two major capacitance sources: the dielectric and the polysilicon. When in contact with conducting materials or other dielectrics, semiconductor bands bend, resulting in an electron-depleted region near the interface, between poly and oxide. This region is 6-8 Å thick and, lacking conductors, is a dielectric. Now there is 10-12 Å equivalent of dielectric, plus 6-8 Å of poly. "Companies are searching for an oxide that, once the poly depletion effect is extracted, goes from 12 to 10 Å," Meissner said. "They're willing to revolutionize everything for 2 Å. If you eliminated the poly, you'd be rid of 6 Å— hence metal's desirability. The likeliest scenario is a poly gate on high-k, followed by the introduction of metal for a 90 nm low-power application. This can be done if the high-k material is thicker. Some want to keep SiO2 at 10 Å and use metal for scaling." Another challenge will result from the decision on logic metal gates. "Even at the lowest level you have a tungsten silicide, so there's silicon but also a metal. Much has been done to prepare for DRAMs with metal gates, but the industry keeps getting by with tungsten silicide," Meissner explained. High-k dielectrics eventually require a metal to prevent depletion. "New dielectric materials pose difficulties — no metal has been found that works well with both n- and p-types, so you end up with two plus the high-k material," he added. The state-of-the-state-of-the-art is application-dependent, according to Marc Heynes, high-k program director for IMEC (Leuven, Belgium). "You have low-power applications targeting 1.4, 1.6 nm EOT and high-performance applications. Obviously, if you want smaller transistors and scaled-down EOT, you do it to get increased drive current, and to get it you need high mobility. However, there are two limitations. One has to do with scattering due to layer charges and instabilities due to charge trapping, the other with remote phonon scattering, which degrades transistor mobility." This is fundamental because it deals with material-intrinsic properties, and the higher k value is related to ionic bonds that cause the phonon scattering. Most hafnium-based materials, except for the hafnium silicates, pose this problem. "This can be solved with an interfacial oxide between the silicon and the high-k layer," Heynes said. "However, this increases the final oxide thickness, causing reliability concerns." Interface control is critical for low-interface trap densities, good layer stability and mobility. Inserting interfacial oxides between the silicon and high-k dielectric is a solution, but there is a price in terms of EOT. Other solutions require silicate materials at the interface, which do not suffer as much from scattering but reduce aggressive scaling while providing the desired leakage current benefits. "Depending on whether you're going in for aggressive scaling and <0.7 nm EOTs for high-performance applications, or for low power where you have 1.6 and 1.4 nm — there are different solutions," Heynes said. "For low power it's silicates and interfacial oxides, which provide good mobility and low leakage. For high performance, you can get low leakage and low EOTs but not enough mobility for improved transistor performance. The electrode materials choice also influences results. You can gain a few angstroms going from silicon to metal gates." Genus' Rust considers gates a moving target. "There's considerable soul-searching about the combination of dielectric and gate materials to come up with new gate stacks. Then there's the whole interconnect scenario, more important for logic and dual damascene, where you require barriers and seed materials." For gates, the effort is reduced to process manufacturability. From the capacitor dielectric side, the choices for current and future generations are clear: aluminum oxide-based dielectrics combined with higher-k materials. "Here we run into integration issues," Rust said. "One either follows the current MIS scheme or an MIM scheme. MIM gives more flexibility by reducing the overall interfacial oxide between the silicon and the dielectric, increasing the k value and giving extendibility with the same dielectric material set choice. You can also consider high-temperature electrodes and use exotic higher-k materials such as ruthenium, ruthenium oxide, iridium and iridium oxide kinds of metal electrodes." Once the material is chosen, the matter shifts to whether there is a production-worthy ALD system. Rust pointed out that ALD is used for sensor heads. "Benefits are in yield — better film quality, improved uniformity, fewer pinholes. It replaces PVD, and it'll carry to the semiconductor sector, particularly for MRAMs, where ALD's quality will gradually encroach on mainstream deposition techniques. For ALD, metrology challenges aren't great. We can measure 3 or 4 Å." By its nature, ALD is digital — it uses discrete pulses. "When you feed gases to a wafer in CVD, it's a question of how long you leave it in there — thickness will increase over time and may not be linear," he added. "With ALD, you expose the wafer and if you exceed the saturation time, you don't grow film. You know your film thickness just by counting pulses." Etch difficulties Advanced memory and gate oxides require new solutions, said Ajay Kumar, Applied's director of emerging technologies etch PBG. "There's a demand for non-volatile data storage for commercial electronics applications." Logic and memory cell integration on the same chip is needed for SOC chips. To achieve this for DRAMs, MIM capacitors, embedded RAM and gate stack, the industry is investigating high-k materials with lower leakage current, high breakdown voltage, and lower EOT. "As SiO2 thickness approaches quantum limits and the gate technology node reaches 65 nm, high-k materials are evaluated to replace SiO2," Kumar said. "The industry is looking for different high-k materials including HfO2 (HfSiOx), ZrO2 ( ZrSiOx), and Al2O3 and lanthanum composites. Implementation requires one high-k material for all memory and gate stack requirements on the same chip." A snag in the high-k materials transition is that electronic properties like high mobility must be achieved in the transistor channel, which is limited by the interface trap density created by the materials. There are also integration issues such as depositing thin stoichiometric layers with acceptable electronic properties, and then removing the Gox without damaging the source and drain area. "High-k material etch presents three complications," Kumar said. "One, their removal in a chemical etch regime. Most of these materials are non-volatile and normally don't form volatile byproducts. Second, avoiding damage to the source and drain layer underneath while retaining sufficient selectivity to mask, as well as not altering the defined gate structures' CDs. Three, engineering a contamination-free, production-proven solution." Applied has developed a dry plasma etch chamber where, using conventional masks, these materials can be etched without gate, source or drain damage. The etches are combined in situ or in an integrated manner, with post-etch treatments to deal with contamination. Limitations drive the migration to high-k dielectrics. Thus, the focus is mainly on HfO2 or ZrO2, with emphasis on HfO2 or hafnium silicate. Some alumina and lanthanum composites also display these properties. These materials are ceramic-like and difficult to deposit because their precursors — chlorine, hydrogen or carbon — can be contaminants. Even if successfully deposited, electrical properties must be considered. High mobility is necessary to avoid transistor channel problems. FSI's Becker believes there will be an implementation of silicated oxides, possibly at the 100 nm node. "When fabricating the transistor, you plasma-etch to define the gate electrode and stop on the gate dielectric. Wet etching is then used to remove the gate dielectric from the source and drain regions, because continued plasma etching lacks selectivity to the underlying silicon and would cause severe damage. However, new high-k materials' etching rate is so low in traditional HF mixtures, and selectivity to other oxides so poor, that the rest of the transistor is destroyed while removing it. Adding nitrogen to the high-k material improves etching rate, but it's still too low with traditional room-temperature HF mixtures. Silicated HfO2 and silicated ZrO2s also etch too slowly in traditional room-temperature HF mixtures." (Fig. 2)
2. Silicated oxides will probably be implemented at the 100 nm node. High-k etching requires that the gate electrode be defined, and that it stop on the gate dielectric, without gate undercut. (Source: FSI International)
FSI has a chemical formulation it believes provides a solution for etching these silicated HfO2s, providing the needed selectivity in a reasonable amount of time, with reasonable results. For Les Jerde, director of technology for Tegal (Petaluma, Calif.), the main concern is which materials provide the dielectric constants needed. "There's been noise around Ta2O5, which we view as a one-generation material." The issue for these materials — HfO2, for instance — is etch: what to do with volatile end products, and how effective plasma can be in avoiding damage to devices downstream. "Controlling densities in the systems and dealing effectively with them to avoid ongoing, recurring damage downstream is critical. In gate applications, damage often results from ion bombardment," Jerde said. "We have a dual-frequency reactor technology that controls ion energies, particularly at the ion-energy scale's low end. We can access <20 or <30 V ion energies and control them in that range. If you choose chemistries intelligently, you can maintain acceptable etch rates, avoid damage, and achieve high selectivities." Tighter critical dimension (CD) control is required at 90 nm and below, said Yung Kim, senior product marketing manager, Global Products Group, at Lam Research (Fremont, Calif.). "Current ITRS specifications for total variation are 10% or less between lithography and etch, with over 65% of the budget allotted to lithography. Because of etch process parameters' interdependence, one variation-reducing strategy is identifying those parameters that can be independently controlled, known to affect CDs." High-k integration has shifted from the 90 to 60 nm technology node and below because of difficulties in material properties and interface quality. "The promising high-k materials — HfO2, ZrO2, and their silicates — aren't a hurdle to etching the gates themselves, stopping on the high-k dielectric," Kim said. "Integration challenges involve removing non-volatile high-k dielectric materials: controlling silicon recess, removing sidewall deposition and ensuring final structure integrity." To remove these materials, dry etch process requirements are primarily physical, not chemical, and achieving high selectivity to silicon is challenging. Low etch rate and undercut are primary problems with wet etch approaches. Thus, process approaches combining wet and dry etch strategies will be required. "We expect single- or dual-metal gates with high-k dielectric integration for advanced memory and logic applications for the 65 nm and below technology nodes," Kim said. "This will increase etch challenges for controlling uniformity, microloading and selectivity, as well as for high-k removal. Process tuning capability that eliminates parameters' interdependence and step-by-step control will be required." Film measurement "Optical ellipsometry is running out of steam," said Murali Narasimhan, senior director of marketing, Films and Surface Technology Division, at KLA-Tencor (San Jose). "Metrology's biggest problem is that high-k films cannot be measured solely through optical technology. Airborne molecular contamination deposits a thin hydrocarbon layer on the film, artificially boosting thickness. It's hard to differentiate that film from the underlayers, so you get a combined result and really don't know what's the correct thickness." Electrical methods are unaffected, and are gaining ground in characterizing and in gate oxides' in-line control. Another advantage of electrical methods is that they correlate better to EOT transistor electrical measurements. The dielectric layer's capacitance can usually be correlated to optical thickness. While this works with a well-behaved and well-understood film like SiO2, once it is nitrated to increase the k value, the correlation breaks down. "Leakage plays an important role when gate thickness is &lt;30 Å," Narasimhan said. "For low-power applications, conserving battery power is important, making gate leakage characterization critical. The problem is accurately measuring these films' capacitance and leakage and, when nitrating them, the amount of nitrogen being incorporated and where. There's no technique available to show the nitrogen's location. An electrical response enables a determination about how much nitrogen is implanted and its relative location in the film, based on the electrical signature." "Laser ellipsometry can accurately measure the thickness of nitrided gate dielectric films, but both thickness and nitrogen concentration must be known to provide real-time nitrided gate process control," said George Collins, vice president of marketing at Rudolph Technologies (Flanders, N.J.). Measuring nitrogen concentration is complex because the optical response to nitrided films is practically identical to that of SiO2 in the visible and UV regions. However, nitrogen concentration in ultrathin 15-20 Å nitrided films can be accurately determined through sensitive and repeatable reflectance measurements in the DUV between 190 and 200 nm. "Laser ellipsometry/photomultiplier DUV reflectometry results for <20 Å films show excellent correlation with XPS for thickness and nitrogen concentration, and equivalent oxide thickness using electrical measurements," Collins said. "This technique offers high throughput and repeatability, and small-spot optical metrology capable of nitrided gate process control." More now than ever, OEMs and users must share what they do and how they are doing it, and closely work together. We are going to need to know more about differences in the depositions of these materials, and the types of structures that are going down and how they are going down. All of this affects etch, particularly as features get finer. A whole new level of cooperation will be needed.
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