### From Semiconductor Internantional Nov. 2003

High-k Awaits (and Awaits) Implementation
Alexander E. Braun, Senior Editor -- 11/1/2003
At a Glance
Gate capacitance requirements are driving process engineers to consider high-k dielectrics, which allow thicker layers. If SiO2 continues to be used, in 10 years, gate dielectrics may have to be three monolayers thick. However, high-k integration poses costly problems.
Sidebars: 3-D Structural Metrology Confronts Measurement Uncertainty
A high-k dielectric is an insulator with a dielectric constant (k) higher than SiO2's 3.9. Although nonconductive, when placed between metal plates, these should still be able to interact through electric fields. Although this makes it ideal for structures such as gate dielectrics and capacitors in MOS devices, as well as for very high-density DRAMs, designers attempting to integrate it into high-performance devices often feel as if they are walking across a minefield. "All high-k problems have been solved for thicker films in low-power applications, save one: the PMOS device's anomalous threshold voltage shift," said Gregg Higashi, chief technology officer for the front-end products group at Applied Materials (Santa Clara, Calif.). "People debate its cause. Some hold that it's related to a fixed charge, others that it's a kind of Fermi-level pinning. Metal gates may offer a solution, because the problem seems related to a polysilicon/high-k interaction. However, when it comes to metal gates, the technology's immature." Jeff Butterbaugh, chief technologist at FSI International (Chaska, Minn.), remembers when surface preparation and thin-film removal for cleaning and post-etch residue removal was not an issue. "High-k is extremely resistant to these etching chemistries, and difficult to remove from the source and drain areas. We've been considering chemistries and processing conditions to remove it without attacking the polysilicon gate or etching too much of the SiO2 in the isolation trenches surrounding the transistor." "High-k materials are more complex than we first thought when we set off to integrate them," said Murali Narasimhan, senior director of marketing, Films and Surface Technology Division, at KLA-Tencor (San Jose). "Considerable work remains to be done in process technology and metrology techniques to monitor it." R&D and high-k When a high-k film is thick enough, interfaces can be tailored to obtain good mobility, dielectric constant (Fig. 1 ) and leakage. With thinner films, when a high-performance device designer looks to scale effective oxide thickness (EOT) to <10 Å, there are problems related to transistor mobility and drive current. "The point's to get more drive current and better transistor scaling," said Applied's Higashi. "If you lose drive current due to mobility degradation, you've failed." In the thick regime, needed for low power, this is a challenge. "In the thin regime, manufacturers have achieved much in terms of oxide or dielectric leakage reduction, and reliability. However, we're far from solving all high-performance application problems."
1. Semiconductor devices are designed with a specific gate capacitance, proportional to the dielectric constant, and inversely proportional to the gate material’s thickness. If the gate dielectric were to remain SiO2, in 10 years its thickness would be only 10 Å. Alternative high-k dielectrics enable thicker layers. (Source: n&k Technology)
The removal quandary High-k film removal is a hurdle. "We worked with SEMATECH," said FSI's Butterbaugh, "to find processes and chemistries for post-etch residue removal after the poly-gate etch stops on the high-k material, as well as removal of high-k material from the source/drain area. With a SiO2 gate, this works because most cleaning chemistries remove some SiO2." High-k materials, however, are resistant to these chemistries. "We began looking at chemistries and processing conditions that remove high-k films from the source/drain area, leave the polysilicon gate untouched and won't etch too much of the SiO2 in the isolation trenches surrounding the transistor," Butterbaugh added. "Finding a wet chemistry that works is a predicament." Presently, the high-k focus is on hafnium and some hafnium silicates, including those with nitride in the film. Butterbaugh believes these films are easier to wet etch than pure HfO2. Even with a dilute HF, usually employed to remove SiO2 from the source/drain area, fairly high temperatures are needed to get the HfxSiyOz to etch, and HfO2 films still do not etch well. "It's a selectivity issue," Butterbaugh said. "Concentrated, high-temperature HF removes HfO2, but also SiO2. Some people are looking at ways to remove high-k material from the source/drain using a combination of dry plasma etch followed by a wet etch." With thinner high-k films, complexity declines — it becomes unnecessary to etch for long, and uniformity may not be an issue. "Manufacturers are putting down 30 or 40 Å films," Butterbaugh said. "But much depends on the integration scheme. Some don't think that HfxSiyOz films will be implemented for transistor manufacture until the 45 nm node; others say sooner." By then, some structures may have changed. Some are considering FinFET structures; others a damascene-type gate to avoid depositing high-k materials directly over the source and drain. Metal gates may be used — work proceeds with tantalum, titanium and ruthenium. Chemistries used for back-end-of-line cleaning will likely be used to remove post-etch residue for those types of gate materials. These probably will not tolerate standard RCA chemistries used with silicon and SiO2. "A consideration in surface preparation is that, with the shrinking of the gate electrode width —<50 nm — it becomes susceptible to damage during megasonic cleaning," Butterbaugh said. "When people stopped using megasonic energy, they increased the amount of oxide etched on the surface, because you can remove particles without megasonics by etching and undercutting. Now, ICs cannot tolerate that much etching, so we're also reducing the etching that can occur during cleaning. We're developing methods and processes that do particle removal at both low damage and low etching." Deposition question Werner Rust, executive vice president of worldwide sales and management at Genus (Sunnyvale, Calif.), sees Al2O3 as a high-k starter. "Al2O3 properties lend themselves for integration both for semiconductor and thin-film head applications." Discussions are underway on how to deposit it, he added. "Both capabilities are necessary — the ozone and water processes — but require different expertise. They work at different temperatures and have different demands in getting the species to the wafer." Rust does not view atomic-layer deposition (ALD) as a main player yet because it is slow. "MOCVD, pulse CVD, etc., address this, and materials such as Al2O3 are being researched. There's more than one driver toward production implementation. One is k value, but there are other requirements to solve — conformity, for example. Some thick-film applications lack steep topographies; thin films don't. So when manufacturers go to ALD, they look at the new material and superior conformity." ALD can also deliver films at lower temperatures than can CVD or MOCVD. This becomes important as manufacturers scale down devices, making low-temperature processing appealing. Manufacturers must learn how to deposit Al2O3, and how to etch to control film parameters — the k value, stress, and possible carbon contamination. "We're seeing a split on the DRAM early adopters side: Most suppliers use stacked capacitors, which means that, to increase storage in less space, the k value, the surface area, or both must rise," Rust said. "In the stacked arena, increasing surface area is problematical: they're running out of steam and must move to higher k faster." According to Rust, this is measured by the early adoption of ALD and high-k, implemented at 110 nm, with trench adopting it at 90 nm. Precursors are key to ALD. "From early on, we switched from solid to liquid precursors," Rust said. "ALD will always suffer of low throughput, and the one knob it has is getting species faster to the wafer. Vapor pressure helps, while liquid sources give more molecules than solids on the wafer." Chemistry, not hardware For Vahid Vahedi, director of silicon technology at Lam Research (Fremont, Calif.), it is unclear whether integration problems will allow high-k to be introduced at 65 nm, or delay it until 45 nm. "The industry's moving to hafnium-based high-k films," he said. "Film thickness on the order of 20-50 Å, and when it's removed — particularly in a dry etch chamber — it doesn't form volatile products that desorb from the surface, so you must sputter it without touching the underlying silicon. The typical specification requires removing <20 or 10 Å of silicon — 10 Å is about three monolayers. We've developed a chemistry to etch high-k films that meets these requirements." Lam is looking at chemical solutions. "We've been using traditional tools that etch polysilicon films, and figuring out innovations on how to use the film and shut down on the underlying silicon without resorting to hardware changes," Vahedi said. "With the new chemistries, users can utilize their current polysilicon etch toolset for high-k removal. Etch issues are minor; the challenge for our customers seems to be high-k material integration." Deposition, etch and defects John Almerico, marketing director for advanced products at Tegal (Petaluma, Calif.), recalls his company's first encounter with high-k materials when considering advanced DRAM capacitor structures with BST as an alternative dielectric for post-capacitors. "The high-k material could reduce the DRAM capacitor's complexity and size," he said. "However, facing the risk of going into volume production with new materials, manufacturers resorted to tried-and-true complex oxynitride and Ta2O5 structures, shying away from high-k integration." High-k is being considered for multiple applications. "Let's say, with floating gate structures, the problem faced with these materials and their lack of volatility is that, when dealing with conformal steps where deposition goes down a vertical wall — certainly in a dry methodology — they're almost impossible to remove," Almerico said. "There isn't enough spontaneous chemistry to allow any sort of an isotropic etching component. This must be factored at the cell's design. To isolate structures with the desired topography, the material on these vertical surfaces must remain in place. If considered during design, it can be dealt with; otherwise, we don't have a magic bullet — it's an anisotropic etch." At the gate level, the question is how to remove a hard material like Al2O3 or HfO2 without damaging the shallow junction structures underneath. Applied Materials has described a solution using a dry plasma etch chamber and conventional masks, enabling the new materials to be etched without gate, source or drain damage. It addresses aggressive requirements on 15 Å HfSixOy/HfO2 films with <10Å substrate loss. Looking at metrology KLA's Narasimhan observed that nitrogen in films is increasing. "Manufacturers are moving to plasma nitridation, where they use energetic nitrogen species to almost implant nitrogen into the thin base oxide. Film metrology done with ellipsometric measurements made sense with pure oxides or even lightly nitrided oxides at 130 nm, but now ellipsometry is insufficient." An ellipsometer can monitor the base oxide, because its properties are well understood. When doped with nitrogen, optical properties change, becoming a function of the material's nitrogen content. "The bad news is you cannot use a single-wavelength ellipsometer because the refractive index isn't constant as it was for oxide," Narasimhan said. "And if thickness also changes, you have two variables and multiple wavelengths become necessary." The good news is that it is possible to use variations in the refractive index, and correlate them to nitrogen composition changes. "While simple in theory, this isn't in practice. With very thin films, it's difficult to obtain information from the nitrogen," Narsimhan said. "You need DUV spectroscopic ellipsometry (Fig. 2 ). We have instruments that can scan at the 190 nm wavelength and measure ARC (antireflective coating) layers, for example. The technology affords multiple applications — a big plus for gate applications." Advanced algorithms are used with optical spectroscopic ellipsometry to independently obtain thickness and nitrogen percentages. These measurements are quick, non-intrusive and non-destructive, and can be used on product wafers.
2. Complex process integration challenges at the 90 nm node require constant monitoring of film composition and thickness in production to alert to variations that can impact yield and reliability. Too much nitrogen degrades mobility; too little results in increased leakage and boron penetration into the gate dielectric. E-beam technology and X-ray detectors can determine the nitrogen dose in each wafer, enabling a quick recovery from process excursions. (Source: KLA-Tencor)
Manufacturers also want electrical measurements. It is not only the equivalent oxide thickness that determines capacitance; leakage is also important. Initially, nitrogen was added at the 180 and 130 nm nodes to prevent boron from penetrating from the gate electrode to the channel, causing mobility degradation; this provided a boost in terms of leakage performance. Now nitrogen use is increasing — not just because it acts as a diffusion barrier for the boron, but also because it lowers the CMOS device's operating leakage level. "Leakage characterization is important, and we're seeing an increasing adoption of the corona oxide semiconductor technique to measure leakage," Narasimhan said. "This gives both the EOT and leakage." There is a third class of metrology for composition control, using a semi-analytical technique like X-ray photoelectron spectroscopy (XPS). This is required when facing yield-disruptive issues caused by nitrogen fluctuations. "To recenter their process and establish the right composition, engineers must measure composition directly, not a correlated measurement like optical or even electrical," Narasimhan said. "Although these other measurements correlate to optical or electrical changes, they don't show how much nitrogen is present. X-rays make it possible." Measurement complexity is increasing. "Designers are talking about capping layers with gate electrode as it comes out of the process reactor," Narasimhan said. "So in-line measurements must be done under the gate electrode." Different methods give different responses. Optical methods have more difficulties measuring an ultrathin gate dielectric material underneath a metallic gate electrode, because metals tend to be opaque and transmit little light. With the electrical method, there is an electrical conductor on top of the insulating gate, so one must deal with electrical disruptions in the circuit. X-ray-based methods offer promise, since X-rays from the gate dielectric material can pass through the overlying metal gate electrode and be detected and reliably measured. n&k Technology (Santa Clara, Calif.) has had success in high-k measurement, using high-resolution broadband spectrophotometry with proprietary all-reflective optics over a 190-1000 nm wavelength range, applying the Forouhi-Bloomer dispersion equations and proprietary algorithms. The method simultaneously and non-destructively determines film thickness, refractive index (n) spectra and extinction coefficient (k). High-k film structures such as HfSiO2/SiO2/Si substrate, TiN/HfSiOx/Si substrate, and SiGe/Si/SiO2/Si substrate fall within the technology's capabilities. For high-k structures such as ultrathin nitride and oxide substrates, it is possible to determine whether the nitride is inhomogeneous and if its deposition is dependent on the underlying oxide. Many are trying nitrided ultrathin oxides, according to George Collins, vice president of marketing for Rudolph Technologies (Flanders, N.J.). "Manufacturers have been doing <20 Å lightly nitrided oxides (1-3% range), mainly to affect transistor performance and charge trapping. For truly high-k, you must go to 20-30% nitrogen with a metrology that delivers thickness and nitrogen concentration. With multiple-wavelength ellipsometry, we're getting better than 0.06-0.08 Å repeatability." Two years ago, International SEMATECH (Austin, Texas) concluded that ellipsometry, or optical metrology, might be incapable of delivering the process control needed for nitrided high-k gate mate-rials. "XPS was proposed as an alternative," Collins said. "It seemed to provide the accuracy and repeatability needed to control nitrogen concentration in very thin doped oxide films or high-k films, such as HfO2, in up to 20-30% concentrations. Optical didn't appear to deliver the nitrogen concentration repeatability needed, but a slow vacuum technique like XPS isn't fast enough to provide process control." Since then, Rudolph has developed an optical technique suitable for process control using DUV reflectance measurements. At wavelengths <230 nm, optical dispersion between the oxide and the nitride appears, and the critical information is available below 195 nm. "We've obtained excellent accuracy and repeatability across a range of 3-30 atomic percent of nitrogen concentration with films thinner than 15 Å," Collins said. "With our DUV reflectometer, we have almost perfect correlation with XPS and electrical measurements." Most work today is focused on HfO2, whose k is ~40 — 10× higher than oxide. In theory, one could have a gate 10× thicker with HfO2, so a 50 Å HfO2 gate would give the same performance as a 5 Å oxide gate. "A challenge is that HfO2 has a different lattice spacing than the silicon substrate," Collins said. "Two SiO2 monolayers would be required as a buffer, to accommodate the lattice spacing difference between silicon and HfO2. Our metrology can measure this 5-7 Å buffer layer repeatedly under 40 or 50 Å of HfO2, or other high-k material." Conclusions Is high-k coming? Yes. When? Well, the current situation is reminiscent of what occurred with low-k materials: Originally, the International Technology Roadmap for Semiconductors (ITRS) predicted they would arrive much earlier. However, manufacturers could not decide which low-k film to use, making it difficult to focus on a particular film and work out the chemistries involved. As difficulties appeared, workarounds were done. Designers are now figuring ways to get by without high-k materials. This will continue until the technology is ready to be inserted. Meanwhile, the requirements for these materials will continue to be pushed out.
For more information...
When you contact any of the following manufacturers directly, please let them know you read about them in Semiconductor International.
Applied Materials http://www.appliedmaterials.com/ | FEI Co. http://www.feicompany.com/ | FSI International http://www.fsi-intl.com/
Genus http://www.genus.com/ | KLA-Tencor http://www.kla-tencor.com/ | Lam Research http://www.lamrc.com/
n&k Technology http://www.nandk.com/ | Rudolph Technologies http://www.rudolphtech.com/ | Tegal http://www.tegal.com/
### 3-D Structural Metrology Confronts Measurement Uncertainty Steven Berger, Vice President and COO, and Prasanna Chitturi, Director of Metrology Products, FEI Co., Hillsboro, Ore. Measurement uncertainty — caused by shrinking geometries, new materials and composites, warpage from larger wafers, denser pattern stacking, and an increased number of process layers — has called into question the usefulness of traditional metrology and yield management practices.
1. Automated cross-sectioning and metrology of gate step coverage. (Source: FEI)
Automated dual-beam systems allow for statistically meaningful cross-sectional data to be gathered in real time. Using high-resolution SEM imaging, the automated cross-sectional approach allows for high-precision measurements of gate CDs down to 45 nm. Furthermore, for high-aspect-ratio gate structures, step coverage of the isolation dielectric on either side of the gate can be measured (Fig. 1 ) to ensure that switching speeds are not compromised. Until the advent of high-throughput in-line cross-sectioning, this data was not available in a statistically meaningful manner Normalized step coverage data in Figure 2 shows that the left and right step coverages vary considerably across the wafer. In current fab practice, gate step coverage is not a monitored metric. One can see the result of this in the data plot, where the deviation from mean is substantial. Moreover, the data shows that the left and right step coverages vary considerably from each other at several points across the wafer.
2. Normalized variation of gate step coverage across the wafer. (Source FEI)
Leading-edge fabs are now focused on the use of dual-beam systems for line monitoring of gate structures for 65 nm nodes and below.

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