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Cover Story | January 2001
Ramping the 0.13 µm Generation
| At a Glance |
With 193 nm lithography in development, copper interconnects entering production and 300 mm at the pilot line stage, producers of 0.13 µm devices are facing formidable and unprecedented challenges. Significant issues include mastering 248 nm lithography enhancement and 193 nm introduction, electrically identifying yield detractors in copper damascene and effectively integrating low-k dielectrics.
Laura Peters, Senior Editor The industry's technology-driven transitions to 0.13 and 0.10 µm are exceptional because of the simultaneous move to 300 mm wafers, an economically motivated transition. In light of remaining process uniformity and automation challenges, several device manufacturers will transfer their more mature, 0.18 µm processes from 200 to 300 mm first to minimize risk. "The rate of 300 mm adoption depends largely on the issues device manufacturers encounter while ramping 300 mm and 0.18 µm," said Adrian Kiermasz of Lam Research Corp. (Fremont, Calif.). Although 248 nm lithography will be used across the board for the first generation of 0.13 µm devices, 193 nm systems must be adopted soon thereafter. Likewise, oxide-like interlevel dielectrics will fill the needs of the first-generation 0.13 µm devices, but low-k materials may be required for subsequent shrinks. Copper, still in its infancy with issues of voiding, scratching and corrosion, is keeping engineers busy at these nodes. Adding to that the diverse needs of embedded memory and system-on-a-chip devices, the processing challenges of today are like no other in semiconductor history. The following explores the most critical lithography, deposition, etching, ion implantation, CMP and cleaning challenges of the 0.13 µm technology node. Critical lithography levels Critical levels for the first generation of 0.13 µm devices will use 248 nm lithography, but second-generation devices will likely require three to four critical levels that may only be patterned using 193 nm lithography. With the transition from 248 to 193 nm lithography comes a shrinking process window and the increasing need to optimize the overall lithography cell to produce the best image, also known as process image integration. "What we see is that every subsequent wavelength of lithography is being inserted at a lower k1 factor, resulting in stronger and stronger interactions between various aspects of the lithography process — pattern transfer from the reticle to wafer, effects of the photoresist, lens aberrations, and the impact of OPC and phase-shifting enhancement techniques," explained Kurt Ronse of IMEC (Leuven, Belgium). "So there is an exponentially increasing amount of work to be done up-front to characterize and understand these lithography processes, but less and less time to do it in." Interestingly, while many industry observers point to a lack of readiness for 193 nm resists as a key cause of a slow transition to 193 nm lithography, Ronse points out the limited availability of production-ready 193 nm scanners hinder faster adoption just as much. "The leading-edge fabs each have a few 193 nm scanners, but they'll have to wait until the 0.10 µm generation for production volumes to become available." Regarding the extendibility of 248 nm in the meantime, Ronse said, "With the high-NA scanners on the market today and the enhancement techniques at our disposal, 248 nm lithography can meet the needs of the 0.13 µm generation (0.10 µm features). In certain special applications with extremely periodic designs, you might be able to do some critical levels at the 0.10 µm node." Of course, extendibility is a moving target. "With the performance we see today, the second and third generations of 0.13 µm devices will have a substantial number of critical layers that will require 193 nm for gate, active area, contact and via patterning," he said.
1. A SEM of 130 nm transistors patterned with 193 nm lithography, a standard binary mask and no enhancement techniques. (Source: IMEC)
Outstanding issues with 193 nm resists include the need for increased etch resistance, better adhesion and reduced line-edge roughness, "which becomes a significant part of your CD budget at these dimensions," Ronse said. Figure 1 shows the capability of 193 nm lithography without enhancements. With enhancements, the industry expects 193 nm to readily address the 0.10 µm technology, but 0.07 µm devices (with 50 nm critical dimensions) will most likely require 157 nm technology. For both 248 nm and 193 nm lithography, Ronse distinguishes moderate and aggressive forms of reticle enhancements. "Mask shops can fabricate the less complex embedded or attenuated phase-shift masks in one step, like binary masks," he said. "In addition, they are easier to inspect and repair." However, stronger PSMs such as the alternating Levenson-type masks require more complex conversion of the data and reticle processing, which leads to slower mask turnaround time from days to weeks. The demands of fast-turnaround prototyping still cannot be met with this approach in most cases. "There are also different levels of aggressiveness you can apply with OPC," he added. OPC essentially widens the process window of manufacturing at a given illumination wavelength. One significant difference between the 0.18 and 0.13 µm generations is the increasing use of hard masks, especially in back-end-of-line (BEOL) processing, according to Kiermasz. "The hard masks are being used because the metal lines are getting closer together and aspect ratios are changing, so you are effectively losing resist selectivity," he explained. The behavior of the resist is also very different between 248 and 193 nm chemistries. In etch, Kiermasz emphasized a movement to more complex stacks. For instance, for DRAM gates (nitride/ tungsten/WN/poly), shallow trench isolation (STI) or dual-damascene dielectrics, "your system has to be designed to rapidly change etch chemistries, selectivities, remove the gas from the previous etch, ensure a low residence time, and carry on with the next etch," he said, adding, "You need to maintain uniform gas flows, control ion flux and plasma distribution, and every wafer must see the exact same chamber condition." Such stacks are driving a requirement for better multilayer metrology methods. "We're finding that an acoustic method that has a time delay between various layers in the stack may prove important in monitoring complex stacks," said George Collins of Rudolph Technologies Inc. (Flanders, N.J.). Yield management Tom Long of KLA-Tencor Corp. (San Jose) sees the top challenges in front-end-of-line (FEOL) parametric improvement relating to CD, shallow junction, gate oxide thickness and charge and defect control. "Reticles have become a key technology driver and the ability to inspect them a key enabler," he said. KLA-Tencor's lithography control solution module concentrates on controlling CDs, overlay and defectivity from the reticle to resist and etch patterning. Software advances are also becoming essential to good lithography control. "In order to get the wafer-to-wafer and run-to-run control necessary on critical levels, customers are using advanced process control — taking the last CD or overlay measurements, applying sophisticated algorithms and giving feedforward and feedback information to adjust the process," he said. "With such tight tolerances required in today's processes, customers need a turnkey solution for controlling the whole lithography process." (For more information, see "Addressing 0.13 µm Yield Management Issues.") Defect control at 0.13 µm requires the increased sensitivity of shorter-wavelength inspection tools, utilizing UV or e-beam illumination schemes. With the increased sensitivity, it is essential to utilize defect filtering and automatic classification capabilities to isolate yield limiting defects from non-critical defects, Long said. Transistor scaling Transistor scaling is leading to the consideration of alternative gate dielectrics and gate materials, more ion implants to tweak transistor performance and a move from titanium silicide contacts to cobalt silicides. However, advances made with conventional materials are delaying the monumental change to alternative materials, though scaling is expected to hit a wall at the 0.10 µm generation. Many solutions are being pursued (Table) to address scaling issues, including short-channel effects and poly depletion.

Table 1. Possible Solutions for Scaling Beyond 100 nm

Category | Description
Channel engineering | Channel epitaxy, short-channel effect (SCE) and junction capacitance (Cj) improvement. Reduced Vth fluctuation. Strained-Si channel, enhanced mobility and transconductance (Gm). Halo implant optimization. Reduced SCE, junction leakage and Cj.
High-k gate dielectric | ZrO2, HfO2 and silicates Al2O3 and La2O3 TiO2/Si3N4 and Ta2O5 SrTiO3
Gate oxide | Oxynitride using NO. Reduced boron penetration. Reduced Vth spread. Oxide scaling evaluation and optimization
Gate electrode | Poly SiGe gate. Reduced poly depletion, enhanced PMOS performance Poly/metal (Cu, W) stacked gate. Reduced gate sheet resistance. Metal gate (W/TiN) Dual metal gate. Ti for NMOS, Mo for PMOS.
Shallow junction | Atomic layer doping, Si molecular layer epitaxy Low-energy implantation, decaborane implantation and optimized anneals Plasma doping Laser annealing SiGe extension, silicon cut-off function using SiGe Spike annealing
S/D engineering | Elevated source/drain. Reduced Rs, better SCE, reduced junction leakage. Bandgap engineering. SiGe source/drain. Improved SCE. Nickel silicide. Lower Rsd, improved transistor performance.
Etc. | S/D extension overlap optimization Lower contact resistance using laser annealing
Sub-50 nm CMOS with modified structure | Self-aligned double gate Vertical replacement gate
Source: Samsung Electronics1 |
Pre-gate oxide cleaning and subsequent deposition are undergoing substantial changes as the oxide gets thinner. "There seems to still be disagreement in the industry as to which is the best surface to present to the gate oxidation process," said Jeff Butterbaugh of FSI International (Chaska, Minn.). "On an integrated vacuum platform we are offering a combination of anhydrous HF along with a UV/chlorine type of photochemical process that removes organics and metallic residues." Gate oxide dielectrics are usually nitrided oxides these days, taking advantage of the slightly higher physical thickness of the oxynitride that leads to a shorter electrical thickness (oxide equivalent), created either by nitrided oxidation or RTP nitride following oxidation. The nitride also serves to prevent boron penetration from the doped regions into the gate. Multiple oxide thicknesses on a chip are becoming more common to allow operation at two or more supply voltages. Thin oxides stretch the performance of metrology tools. By combining sensitive reflectometer measurements at 193 nm and a very stable ellipsometer with a HeNe laser, these ultrathin dielectrics can be effectively measured, Collins said, "while affording the opportunity to separate the signals and monitor the nitrogen content of the NO or ONO film." Though ion implantation tool suppliers have worked hard over the last several years to continue to scale S/D junction depth, the trend appears to have reached a practical limit in terms of device performance, especially for p-channel transistors. "We have shown that 0.5 keV boron implants appear to be at the lower useful limit for shallow junctions, not just for 0.13 µm but for all technologies," said Lenny Rubin of Axcelis Technologies Inc. (Beverly, Mass.). "Below 0.5 keV, the implant becomes less productive, more costly, and the final junction performance (simultaneous achievement of junction resistivity and depth) is the same." He estimates that the performance limit with a 0.5 keV boron implant and spike anneal is about 350 Å and 350 W/sq. "To further reduce either metric, the other must go up," he said. Today, rapid thermal spike anneals are beginning to move from the development lab to production, where RTP uniformity and repeatability are most crucial. In addition, Axcelis and other experts in the industry have determined that ramp rate is not a good measure of the quality of a spike anneal, but rather the time spent diffusing the dopant.2 "Since about 90% of the dopant activation really occurs in the short duration from approximately 50deg below the peak temperature to the peak temperature and back to 50deg below, this interval of time is really a better specification," Rubin explained. Axcelis believes that, especially in the case of spike anneals, a hotwalled system that operates in a quasi-thermal equilibrium provides better uniformity. "Using a fast elevator to move the wafer in and out of the quasi-thermal environment also allows us to now achieve a smaller diffusion thermal budget than any conventional lamp-based RTP," Rubin said. Other critical implants For advanced logic devices and embedded memory or system-on-a-chip applications, there is a notable trend to using multiple p and n wells. "The trade-off between power consumption and device speed makes it desirable, for instance, to independently optimize the I/O devices on the periphery of the chip and the logic gates in the center of the chip, leading to two different well designs," Rubin said. Such a trend leads not only to more ion implantation steps in the overall device but also greater use of chained implants performing up to five implants sequentially. To prevent device latch-up and control electrostatic discharge, buried layer implants (~2 µm below the active area) are becoming increasingly common for advanced logic devices. Another method of addressing latch-up that simultaneously reduces the overall power consumption of high-speed devices is silicon-on-insulator (SOI) technology — forming an oxide layer beneath the active area either by SIMOX (separation by implantation of oxygen) or bonded wafer approaches. The SIMOX process implants high doses of oxygen (to 1E18 atoms/cm2) followed by a high-temperature anneal. "The proposed solution for thinning oxide gates has long been high-k dielectrics but, unfortunately, these new materials may not be ready in the timeframe required by aggressive roadmaps of some companies in the next two to three years," said John Pope of Axcelis. In the meantime, companies may use SOI technology to continue scaling because "you can effectively get the same performance from a 0.10 µm SOI device as the equivalent 0.07 µm device built on bulk silicon," he said. Although many companies made the transition from TiSi2-based self-aligned silicides (salicides) to cobalt-based salicides at 0.18 µm for better control over contact resistivity at shrinking lateral dimensions, another material change looms. Nickel silicides may be used as soon as the 0.10 µm generation. Front-end CMP processes include STI CMP and pre-metal dielectric (PMD) planarization. Customers and tool suppliers are working on direct STI CMP processes, though the reverse mask approach prevails in manufacturing because of the diverse array of pattern density on today's chips. Nitride erosion budget is also shrinking. Greg Amico of Applied Materials (Santa Clara, Calif.) said that some processes call for nitride loss of less than 200 Å on an 800-1000 Å film. STI CMP also demands the lowest levels of defectivity, next to PMD CMP, where microscratching and overpolishing significantly affect yield. In-line thickness metrology is becoming mainstream for STI and PMD CMP processes, with closed-loop processes becoming available for across-the-wafer uniformity control. Memory cells Stacked capacitors push the envelope of dielectric etching to produce 20:1 aspect ratio (AR) features, with the trend possibly increasing for future devices. In addition to stacked capacitor scaling dictated by DRAM memory density, system-on-chip designs introduce new challenges for dielectric etch, particularly high aspect ratio contacts with multi-level stops. Diana Ma of Applied Materials added that, to be successful, "we need to ensure a large process window for etching >10:1 aspect ratio contacts with high selectivity and also a production-worthy etch stop margin." Capacitor design innovations will extend the usefulness of current materials as much as possible, but an eventual shift to new materials is necessary to maintain memory cell capacitance at ~30 fF.3 At 0.13 µm, 1 Gb DRAMs are being produced using NO capacitor dielectrics and hemispherical grade silicon. But at the 0.10 µm generation, a change in capacitor dielectric to high-k materials such as BST is likely, with an associated move to metal capacitor plates, possibly platinum or iridium, with their oxides or silicates used as barrier materials. "Some people were evaluating iridium, but it has had stability issues," said Jim McKibbon of Tegal Corp. (Petaluma, Calif.). "One key issue with these new materials such as cobalt, iridium, nickel and others is the need to prevent metal corrosion after etch, since halogen gases such as fluorine and chlorine have to be used." Etchers must also have precise high- and low-temperature control. For instance, magnetic RAM structures used in GMR devices cannot tolerate temperatures above 150° or the spin state may change. Interconnect processing The effectiveness of copper, barrier and seed process modules are largely a result of the material chosen for low-k interlevel dielectric (ILD), according to Dana Tribula of Applied Materials. "The ability to eliminate the etch stop between the trench and via dielectric as well as the use of hard masks are decisions that largely depend on the customer's dielectric scheme," she said. With different low-k materials, she added, one gets different etch profiles, undercut can be more of an issue if hard masks are used, and the adhesion of the copper barrier metal to the ILD depends on material properties. Dielectric and copper CMP are vital to the fabrication of logic devices with up to eight levels of interconnect. Most companies are using intermediate dielectric polishing steps with copper polishing, adding multiple processes for each layer patterned, an approach that is becoming increasingly necessary. "Despite its challenges, the problem of polishing copper on FSG or oxide is actually easy compared to polishing copper on low-k dielectric," said Fritz Redeker of Applied. "Because the low-k material's interfacial adhesion is typically less than that of FSG, you have to worry about damage and moisture penetration — issues you didn't have to the same degree as before." On-board polished endpoint metrology goes a long way to controlling wafer-to-wafer topography, he said. "We can also go to very low pressures, use stiff pads and use more chemically active slurries to polish copper damascene structures embedded in the low-k materials." Low-k dielectrics The greatest outstanding question at the 0.13 µm generation, just as it was at this time last year,4 is whether low-k dielectrics with sub-3.0 k value will be used in production and, if so, which material will be used. For leading-edge logic device manufacturers, FSG with nitride etch stops will be used at 0.13 µm, replaced with spin-on hydrocarbon films or silicon oxycarbide (OSG) films with SiC-based stops at 0.10 µm, beginning integration as early as the second half of 2001. Among memory and non-leading-edge logic manufacturers, many companies are integrating copper with SiO2 for the first time at 0.13 µm. The implementation of low-k dielectrics in the dual-damascene structure presents tremendous integration challenges for dielectric etching, barrier metal and copper. Nitrogen groups also negatively interact with deep-UV resist. "Our first generation of silicon oxycarbide films were deposited using nitrogen gas, which caused footing," explained Wilbert Van den Hoek of Novellus (San Jose). "But the larger challenge was the result of amine groups being absorbed into the film during dep, etching or stripping, causing via poisoning." He said that it has become very important to remove nitrogen from all these process steps.
Click for full size image
2. Sampling of the many challenges of integrating low-k dielectrics in a copper dual-damascene process flow. (Source: Lam Research Corp.)
"Some of the challenges in low-k integration include resist faceting, copper sputtering, the need to maintain vertical profiles, and possible device damage during the barrier open step," Lam's Kiermasz said. Figure 2 illustrates many of these integration challenges. "We've found that a dual-frequency capacitively coupled reactor able to control ion distribution and dc bias best meets the needs of dielectric low-k stack etching." Applied's Ma emphasized the importance of optimized low-k processing, saying, "Plasma chemistry and reactor design are key to attaining the selectivity to the underlayer. However, we view the resist ash and post-etch clean processes as the critical, influential steps affecting the effective k of the interconnect. To this end, we have observed the necessity of an equal focus in the ILD etch and resist ash/clean steps during process optimization to prevent bowing of the etch profile, and to preserve the k value of the film." When device manufacturers eventually go to porous low-k dielectric films for k<2.5, she said, chemistry will be all-important for creating a stable ILD. Once an effective low-k film is deposited, the k value must be maintained through subsequent processes within about 5%. Ideally, of course, companies would like to push the low-k delta to zero. "Each low-k material is different in its interaction with etching, stripping and cleaning, and the types of residues formed," explained Graham Hill of Gasonics (San Jose), a company that is undergoing merger plans with Novellus. In addition, k value differs between in-plane (lateral) and out-of-plane (along the dielectric sidewall), so precise electrical measurements once the device structure is completed really provide the only effective measure of overall capacitance reduction associated with a given low-k material. Hydrogen-based stripping/resist ashing methods are the mainstay in low-k dielectric processing, and process optimization is "a question of finding the right process conditions, balancing the trade-off between downstream and directional residue removal, and providing precise temperature and pressure control," Hill explained. Low-k ILD cleaning processes are gradually moving from wet chemistries to dry methods. "Specific customers are adopting our cryogenic aerosol high-pressure cleaner for defect removal and yield enhancement in the back-end-of-line," said FSI's Butterbaugh. Although most first-generation 0.13 µm devices are using fluorinated silicate glass (FSG) with nitride etch stops (k=7), a few leading-edge companies may use low-k material with a k value below 3.0, along with lower-k etch stop materials. "Once you've gone to all the trouble of creating a sub-3.0 dielectric film, it makes little sense to elevate the overall k using nitride films for etch stop, for instance," explained Applied Materials' Farhad Moghadam. To optimize the effective k value, many device manufacturers are working to eliminate the etch stop between the trench and via levels, an approach that requires absolutely precise control of etch depth and a tight etch process control window. The low-k dielectric materials of choice for sub-3.0 dielectric constant appear to be Applied Materials' Black Diamond organosilicate material, Coral OSG film from Novellus, Flowfill CVD from Trikon Technologies (Newport, U.K.) and SiLK spin-on low-k material from Dow Chemical Co. (Midland, Mich.). Eventually, companies will replace nitride etch-stop layers and even the dielectric AR coating layers/hard masks (with k~9) with SiC-based (with k<5) films available from Novellus and Applied Materials. Pivotal to extending low-k PECVD of OSG films to ~2.3 is the use of alternative precursors. Novellus uses a different class of precursors for its second-generation Coral film. "It's all a question of what you can put in a precursor to get a lower-k film with the properties you want, without losing the benefits during cracking of the precursor by the plasma," Van den Hoek said. Spin-on low-k materials pave the way for a new metrology application — using inspection methods to determine the completeness of the film curing process. "At first, device manufacturers didn't think such a method would be necessary in-line but just for initial characterization," said Rudolph's Collins. "However, given the speed at which these dielectrics are being brought in, the check on the cure step is desired in production." Metal deposition Typical dual-damascene structures used in leading-edge logic devices with up to eight levels of metal incorporate Ta/TaN barriers that surround the copper on all sides, followed by a seed layer copper deposition and copper electroplating. Optimization of the process is needed to assure adequate barrier metal step coverage in preparation for bottom-up fill by copper electroplating, Applied's Tribula said. Because of copper's maturity relative to low-k dielectrics, she said, these metalization processes are being optimized for productivity and cost-of-ownership while the low-k efforts focus more on integrating an acceptable, high-reliability film. Ionized metal plasma technologies are migrating to the 0.13 µm generation for both barrier metal (TaN/Ta stack) and copper seed deposition. To take the technology to the next generation, Applied Materials is offering enhancements to its ionized plasma platform, including a new ion source and electrostatic chuck design for better step coverage and uniformity. Novellus's Van den Hoek sees ionized PVD extension to the 0.10 µm generation. "However, issues of micro-trenching at the corners of the line etch can lead to problems of inperfections in the seed, but this may be addressed by wet chemical repair as part of the electrofill process." Copper electroplating processes "are all about gap fill," Tribula said. Plating additives are increasingly being used to better fill trenches and vias without voids, and even seams in the plated feature are considered a defect because they can lead to reliability issues, she said. In addition to the significant challenges in barrier layer, seed deposition and ECP fill, copper CMP has its challenges. These include controlling dishing and erosion, and eliminating scratching and post-CMP corrosion — all of which influence device performance and reliability. One solution aimed at providing better planarization is the use of advanced consumables such as fixed abrasive pads. "Through our joint development with 3M, we've determined that fixed abrasives have a lot of potential, for instance, for STI applications," Applied's Redeker said. "But for copper, further development is required." In copper CMP, one must control post-polish corrosion through special wet sequences and passivation methods, and eliminate microscratching, typically by lowering platen pressure and reducing abrasives. "Copper damascene is probably the most complicated CMP process that's ever been done," Redeker said, "and we are pressed to control topography and deliver a solution with a high enough throughput and low enough defectivity level control so that the transition to copper metalization can provide the cost advantages it promises." Copper cleaning often involves the use of specialty residue removers offered, for instance, by EKC Technology Inc. (Hayward, Calif.) and Ashland-ACT (Easton, Pa.). "We've developed a wet chemistry using dilute HF and a controlled level of dissolved oxygen that appears to work well at removing residual copper after dielectric etching," said FSI's Butterbaugh. When it comes to the interconnect, KLA-Tencor's Long emphasized the benefits of combining physical and electrical measurements. "The synergy developed between optical inspection methods and e-beam voltage contrast techniques allows us to correlate electrical defects to physical signatures," he said. "Using voltage contrast, we can take electrical defect coordinates and reidentify them on our SEM review tools — a capability that most other e-beam review tools cannot provide." What about 300 mm? The long-awaited transition to 300 mm wafer processing has finally begun, with as many as a third of the planned fabs today being 300 mm. Despite some remaining processing and automation issues,5 300 mm is nonetheless happening. KLA-Tencor's Long observed that, because many of the particle issues have been reduced in going from modern 200 mm tools to new 300 mm tools, yield issues primarily come down to systematic failures. "Particularly in CMP and etch, we're seeing that some of the uniformity issues have not been solved," he said. "Specific failures are coming from poly stringers left after gate etch, vias or contacts that did not open, and copper damascene problems such as sub-surface voids in the plated copper structure." • REFERENCES S. Song et al, "CMOS Device Scaling Beyond 100 nm," IEEE IEDM Proc., Dec. 2000. A. Agawal, "Ultra-shallow junction formation using conventional ion implantation and rapid thermal annealing," Proc. of the VIIIth Intl. Conf. on Ion Implantation Technology. J. Baliga, "New Designs and Materials Tackle 1 Gb Memory Challenge," Semiconductor International, Nov. 2000. L. Peters, "Who Will Gamble at 0.13 µm?" Semiconductor International, Jan. 2000. "300 mm Begins," Semiconductor International, July 2000.

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