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Outlook on New Transistor Materials
Laura Peters, Senior Editor -- 10/1/2001 Semiconductor International
At a Glance
It has been said that ways of penetrating the red brick walls in the SIA Roadmap almost all involve the use of new materials. But integration issues and the ability to extend the usefulness of existing materials have slowed their adoption. Several new transistor materials will eventually be required, but when?
Sidebars: Photoresist Trimming for Sub-100 nm Gates
Following 30 years of successful scaling of CMOS transistors using SiO2 and aluminum-based interconnects, it is hard to fathom the number of new materials the industry expects to implement in the next 5-10 years. Yet the industry has no choice but to face these materials changes to further advance the Roadmap and allow continued profitability in semiconductors. Still, engineers continue to innovate, modify and improve existing materials, prolonging the adoption of new materials in mainstream CMOS devices. This is especially true at the transistor level, where oxide gate dielectrics and polysilicon are being extended for use to possibly the 50 nm generation (£ 30 nm Leff). For the 70 and 50 nm nodes, IC manufacturers will likely integrate higher-k dielectrics with polysilicon or metal gates. Problems include the lack of industrial consensus on a material of choice (though hafnium and zirconium silicates and hafnium oxide are strong candidates), a lack of tool maturity, and inadequate reliability data on gate stacks with high-k dielectrics. Meanwhile, small additions of germanium to polysilicon gates are helping to increase boron doping levels in PMOS devices and reduce poly depletion effects. As a transition between poly and metal gates, poly stacks with titanium or other metals are promising. Eventually, different metal gates for PMOS and NMOS transistors will be required for optimal CMOS performance, complicating already involved process flows.
1. Silicon-on-insulator wafers, available in a range of thicknesses, can help reduce leakage currents. (Source: SOITEC)
At the 70 and 50 nm nodes, engineers are also considering use of silicon-on-insulator (SOI) technology (Fig. 1), which appears to be on the verge of becoming a mainstream material, expanding beyond high-performance logic, MEMS and power chips. For contacts to the silicon, there is another expected material change from cobalt to nickel silicides to reduce contact leakage and consume less silicon. This change may be required as soon as 70 nm. Adding these to the transitions to copper and low-k dielectric interconnects for multilevel logic devices and the industry suddenly has, perhaps, more change than it can handle. "The introduction of new materials has taken 10-15 years in the past. Now, we are trying to implement multiple material changes at the same time, and it will be very difficult to make them all happen for the 70 nm node," said Ludo Deferm, vice president of business development at IMEC (Leuven, Belgium). Another key factor affecting the evaluation, integration and adoption of new materials is intense technology acceleration. Whereas three years or more once separated device generations, leading-edge companies now follow a two-year cycle, demanding faster integration, reliability studies and yield ramping capabilities. This is occurring while DRAM profits are the lowest in history and all semiconductor devices, even high-end microprocessors and system-on-a-chip devices, are more competitively priced.
2. The key front-end processing challenges are associated with the transition to higher-k gate dielectrics, with an awareness of the metal electrode’s role, formation of ultrashallow junctions and overall process integration of the scaled device with conventional CMOS processes. (Source: International SEMATECH)
Technology acceleration not only restricts the available time for R&D of new materials, it limits access to advanced processing technologies. For example, 248 nm lithography is being extended through image enhancement technologies such as OPC and phase shifting because of cost and less maturity of 193 nm lithography. Once considered a work-around, device manufacturers are using photoresist trimming (see "Photoresist Trimming for Sub-100 nm Gates") to pattern sub-100 nm lines using 248 nm scanners. CMOS transistor scaling Figure 2 summarizes the major challenges associated with further scaling of CMOS transistors. Possible solutions for scaling beyond 100 nm can include the use of raised sources and drains, higher-k dielectrics, metal gates, and Ge doping of gates, channels and S/D (to reduce subthreshold leakage currents). These changes improve transistor performance, addressing short-channel effects (leakage current and threshold voltage stability). Among these changes, the gate/dielectric material change is the most challenging. The ITRS, whose 2001 revision will be published later this year, summarizes the requirements and possible materials changes to the gate stack (Fig. 3). There are many materials options for the high-k dielectric, advanced poly and metal gates. Due to the complexity of the combined challenges, the industry has formed multimillion-dollar partnerships among International SEMATECH, IMEC and device manufacturers worldwide to enable high-k dielectrics and metal gates in the next few years.
3. Possible ways of addressing short-channel effects (leakage and Vt stability) involve new gate electrode, gate dielectric and contact materials. (Source: ITRS 2000)
Gate dielectrics The transition to new gate stack materials can be likened to the low-k interlevel dielectric (ILD) transition, where there is no one material of choice, though IC makers seem to be favoring CVD organosilicate glass or a spin-on organic polymer for first-generation implementation. Even so, many other CVD and spin-on silsesquioxane-based materials are being evaluated for second-generation low-k, 100 or 70 nm devices. Despite the similarity many of these materials have to SiO2, integration schemes and processing of the films are more complex than they were with SiO2. Among higher-k dielectric options, no candidate stands out as the material of choice and the integration schemes will be more complex than they were with oxide and poly. Due to the immaturity of high-k films, companies will continue to use scaled oxides and oxynitrides, but these films are expected to reach reliability limits at ~13-14 Å thick.1 The most likely high-k options are HfO2 (k=26-30) and ZrO2 (k=22-28) and their silicates, although alumina (Al2 O3), titanium oxide (TiO2), yttrium oxide (Y2O3, k=8-15), lanthanum oxide (La2O3, k=21) and combination films are being evaluated. Howard Huff, senior fellow at SEMATECH (Austin, Texas), noted that it is essential that the selected higher-k dielectric for the scaled device be compatible with conventional planar CMOS processes. IMEC's Deferm believes that oxide and oxynitride gate dielectrics will be suitable for 100 nm, and "most likely they will have to be suitable for the 70 nm generation, because we are still in the initial stages of evaluating the high-k dielectrics and some companies want to have 100 nm in production in 2002." Deferm summarized the key challenges associated with high-k material selection. "We need a material with as high a k value as possible that is compatible with both polysilicon and metal gates, has the proper interface characteristics, low leakage currents and suitable reliability, and can be fabricated using a standard transistor architecture." The higher the k value, often, the less compatible the material is with silicon, he added. For instance, Al2O3 films offer the highest thermal stability (1050°C) of all the candidates, but the k value of 8-11.5 is not high enough for use beyond one device generation. However, Al2O3 remains amorphous and demonstrates good interfacial characteristics with silicon. But Huff has noted observation of a negative charge in Al2O3 films and a concurrent increase in NMOS device Vt, which degrades saturation current.
4. A fully depleted SOI approach allows lower leakage currents at shrinking geometries than bulk silicon. (Source: IEDM 2000 and ITRS)
In higher-k materials, just as important as technical performance requirements are such issues as having a reliable tool platform on which to deposit the higher-k material (on 200 and 300 mm substrates), and depositing defect-free uniform films. Atomic layer CVD appears to be a promising process for high-k materials (see "ALD Breaks Materials, Conformality Barriers" for more details) and metal-organic CVD (MOCVD) can also be used. There are also proponents of PVD despite previous presumed limitations related to high-aspect-ratio structures. However, tool platforms and deposition methodologies are immature, especially for use at the gate level. In addition to needing thermodynamic stability on silicon and having an amorphous structure, the higher-k insulator must demonstrate lower leakage current density than SiO2 at equivalent oxide thickness (EOT or teq) and low interface state density (Dit £ 5×1010eV-1 cm-2). The amorphous structure is important because polycrystalline or single-crystal films allow leakage along grain boundaries. The fact that most of the higher-k candidates are oxides also leads to a complication. "High-temperature processing, which is necessary to activate the source and drain junctions, can result in growth of a previously existing interfacial SiO2 film from the preclean process," noted Huff. Whether the oxide film grows depends on the partial pressure of oxygen in the ambient. In all cases, however, engineers must be aware of the possibility of the original metal oxide decomposing into a metal on silicon or a metal silicide depending, again, on the O2 partial pressure. To avoid interfacial oxide formation, Huff noted that companies are trying to reduce the S/D activation temperature (~900°C), but it is unclear whether the thermal budget for this process can be reduced sufficiently while still maintaining the desired transistor characteristics. The option then becomes a new process scheme called "replacement gate," which involves forming the S/D junction in the presence of a dummy gate, which is then etched away, and replaced with a higher-k dielectric and poly or metal gate. Deferm, however, sees replacement gates as a last resort. "This is a complete change of architecture, meaning it also has an impact on design libraries. There are a lot of different approaches but, unfortunately, they all have an impact on the design process," he said. Moreover, Huff noted, the increased cost of ownership is not in line with fab manufacturing goals. Poly/metal gates The industry is debating whether it will be possible to make the high-k dielectric material change coincident with a change from poly to metal gates. As with the copper and low-k interconnect transition, companies would rather change one material per device generation. Many device makers are leaning toward the high-k change as the first choice, integrating it with poly or Ge-doped poly. Ge doping up to ~10% (Si1-x Gex ) represents a fairly straightforward process modification since there are no significant tooling changes. One advantage to metal gates is the elimination of dopant depletion effects that are a big concern with poly. However, for CMOS threshold voltage and work function optimization, two different metals are required. The numerous options for metal gate electrodes include Ta, Ti, Zr, Hf and others for the NMOS and TaN, WN, Mo, Pt, Ir, Ni for PMOS transistors. Key to the selection is compatibility with the dielectric and development of production-worthy deposition and etching/polishing techniques. From a performance perspective, the most relevant consideration is whether the desired device performance and reliability can be obtained without producing unacceptable leakage.2 Also, the gate electrode's work function must be controlled throughout CMOS processing. Optimization requires a balance between the barrier height that controls electron tunneling against the chosen dielectric's k value.2 Gate stacks pose many possibilities — so that the interface with the silicon and the gate electrode can be optimized simultaneously. For instance, one promising stack might be Al/TaN/HfO2/Si. SOI substrates There is ongoing industry debate over whether SOI will ever become a mainstream material for CMOS fabrication. So far, it has addressed niche applications such as producing rad-hard devices. Recently, makers of high-performance logic have begun exploring SOI to help maintain high drive currents while minimizing off-state leakage currents. At the 50 nm node, designers may be able to reduce leakage by 100× relative to bulk-Si CMOS with a 20 nm gate transistor on SOI (Fig. 4). Huff noted, however, that many of the benefits of SOI severely decline with increased scaling. Both Huff and Deferm agree that the utilization of SOI will clearly depend on the device manufacturer's product mix. Meanwhile, SOI quality has improved significantly and the price has been reduced to ~4× that of prime silicon wafers.
References
R. Wallace, G. Wilk, "Exploring the Limits of Gate Dielectric Scaling," Semiconductor International, June 2001, p. 153. R. Wallace, G. Wilk, "Identifying the Most Promising High-k Gate Dielectrics," Semiconductor International, July 2001, p. 227.
### Photoresist Trimming for Sub-100 nm Gates Steve Lassig, Senior Manager, Process Integration Group, Lam Research Corp., Fremont, Calif. Present production lithography processes using 248 nm exposure can yield critical dimensions (CDs) as low as 130 nm at best. More advanced exposure tools and resists, which are just appearing for pilot-line production, can extend minimum CDs to the range just above 100 nm. However, logic applications already require smaller gates. The International Technology Roadmap for Semiconductors (ITRS) indicates a physical gate of £ 90 nm for the 130 nm technology node, and many semiconductor manufacturers are already producing devices with gate lengths of 60 to 70 nm.
The photoresist pattern after lithography (left) and after resist trimming (right) shows that a 140 nm wide feature can be reduced to 60 nm. The resulting profile has less footing and the sidewalls are smoother than the as-developed feature. (Source: Lam Research Corp.)
The industry finds itself in a situation where the resolution requirements for the most advanced transistors are much greater than can be supplied by the most advanced lithography available. One method for closing this technology gap that is finding increasing acceptance is resist trimming. Resist trimming, which will be incorporated in the 2001 ITRS, involves the controlled etching of a photoresist feature on top of a hard mask, followed by etching of the hard mask to produce a sufficiently smaller feature. Controlled, uniform trimming to sub-100 nm linewidths can be achieved by exposing photoresist patterns to O2 plasmas (diluted with Cl2 or HBr) in an inductively coupled plasma etch chamber. Because these systems offer independent control over ion flux and ion energy, nearly isotropic etching processes can be developed to minimize vertical resist loss. While ion energy is reduced, moderate ion acceleration is used to eliminate resist footing. Results (Figure) using a Model 2300 Versys silicon etch system demonstrate that a resist CD can be trimmed from 140 to 60 nm, delivering a CD bias uniformity of <7 nm, 3 σ. Generally, the resulting profile has less sidewall roughness than the as-developed lines. A caveat is that resist trimming does not enable miniaturization of circuits through an increase of feature density. The reduction in resist linewidth is accompanied by a corresponding increase in the spacing between the lines, thereby preserving the pitch. For this reason, the process is usually not employed for DRAM manufacturing. However, reduction of the polysilicon gate length through resist trimming enables fabrication of faster MOS logic circuits and is already in production at several manufacturers' facilities.

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