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A Simulation Study of the Cost and Economics of 450 mm Wafers
Scotten W. Jones, IC Knowledge LLC, Georgetown, Mass. -- 8/1/2005
At a Glance
The well documented difficulties with the 300 mm transition have led some to question whether 300 mm will be the last wafer size and yet the 2004 update of the ITRS calls for 450 mm wafer production in 2012. This article will discuss the results of simulation studies carried out on 450 mm wafer production costs vs. 300 mm wafer production costs.
The introduction of 300 mm wafers to IC production has been long and difficult. Equipment companies made huge investments developing 300 mm tools only to see demand wither during a protracted downturn. 300 mm is only now reaching a position of significance in terms of worldwide capacity, reaching 11.2% in the fourth quarter of 2004,1 and projected to reach ~20% of worldwide capacity on a square inches basis by the end of 2005.2 The well documented difficulties with the 300 mm transition have led some to question whether 300 mm will be the last wafer size. And yet the 2004 update of the International Technology Roadmap for Semiconductors (ITRS) calls for 450 mm wafer production in 2012. At IC Knowledge, we believe the key determining factor for the introduction of 450 mm wafers will be the relative cost of IC production on 450 mm wafers vs. 300 mm wafers. In the balance of this article, we will discuss the results of simulation studies we have done on 450 mm wafer production costs vs. 300 mm wafer production costs. Cost modeling
IC Knowledge has developed a commercial IC Cost Model that has now been in the market since 2001. The model calculates costs by doing bottoms-up analysis of all of the major cost factors in IC fabrication. Modeling begins by selecting one of the predefined processes supported in the model. The process nomenclature is wafer size (mm) linewidth (nm) company process description polysilicon layers metal layers. For each of the more than 200 processes currently supported by the model, we have built a complete process flow and then distilled the process flow down to the number of times each of 50 different standard operations are used in the process. Examples of standard operations would be critical lithography, mid lithography, non-critical lithography, copper CMP, medium-current implant, etc. For each process, we have defined cost, throughput and footprint of the equipment used for the standard operations. Based on the modeled fab capacity and process selected, an equipment set is calculated in the background of the model and total equipment cost, installation cost, cleanroom size and cost, facility size and cost, and facility systems and cost are all calculated. Similar calculations are performed for material, direct labor, indirect labor, equipment maintenance, monitor wafers, facilities and consumables costs. Test and packaging cost calculations are also supported. Recently, we were working on the 0501 revision to the cost model, and we extended the model forecast horizon to 2012 and added factors for 450 mm calculation. Of course, the assumptions that underlie these long-term projections are critical to the 450 mm forecast results we will present here, so we will examine some of the key factors in more detail. Process complexity and die size forecast For our long-term modeling, we have chosen an Intel-style microprocessor process. There are a couple of reasons for this selection. In addition to being the largest semiconductor company, Intel is an early proponent of the 450 mm wafer size. Intel has also been developing new microprocessor processes on a regular two-year cycle and publishing papers on the processes. We have been following this progression for several years, and have used this progression as the basis of our forward projections. With 65 nm production being introduced in 2005, we are forecasting 45 nm in 2007, 32 nm in 2009, and 22 nm in 2012. The specifics of even 45 nm processes are still in development, and we dont pretend to have an ability to make detailed process predictions for 2012, but in aggregate we are more concerned with overall process complexity. We have assumed that high-k gate dielectrics with metal gates will be introduced at 45 nm, and that fully depleted silicon on insulator (SOI) will enter use at 32 nm. The resulting mask and interconnect layers for the forecast processes are compared to the historical Intel process trends in Figure 1.
1. This chart compares forecasted mask and interconnect layers with historical Intel process trends.
To forecast product costs, a forecast of die size is also needed. For die sizes, we have forecast dual- and quadruple-core Pentium 4t die size vs. linewidth out to the 22 nm linewidth. In Figure 2, Pentium (P), Pentium II (PII), Pentium III (PIII), Pentium 4 (P4), dual-core Pentium 4 (P4-2) and quadruple-core Pentium 4 (P4-4) die sizes are shown vs. linewidth.
2. A forecast of die sizes is needed to forecast product costs. Shown here are predicted die sizes for various Pentium products.
Equipment and fab cost vs. output Capital costs have become the single-largest element of wafer fabrication cost, and are expected to continue to increases as a percentage of overall costs. Forecasting equipment cost and cost vs. throughput is a critical element of any model. Figure 3 illustrates exposure system cost vs. year with both forecast and historical data shown. Figure 3 illustrates how equipment costs have been increasing at a fairly consistent rate, allowing forward projection of equipment costs with some degree of confidence that the forecast values are reasonable.
3. Lithography equipment costs have been increasing at a fairly consistent rate, making forecasts more predictable.
Figure 4 illustrates the historical and projected cost for wafer fabs out to a 450 mm fab in 2012. In Figure 4, the blue squares represent the wafer fab cost, with the solid blue squares representing actual data and the empty blue squares representing forecast wafer fab costs. The green diamonds represent the normalized capital cost per unit output, with the solid green diamonds representing actual data and the empty green diamonds representing forecast data. The normalized cost per unit output data takes into account wafer fab productivity improvements due to smaller linewidths, larger wafer sizes and larger wafers fabs on a wafers-out-per-month basis. Notice that, although the cost of wafer fabs is increasing exponentially, the normalized cost per unit out is decreasing exponentially. An easy way to think about the normalized value is that the capital cost per transistor is decreasing, and this continues to be true through 2012 and the introduction of 450 mm wafers.
4. This figure illustrates the historical and projected cost for wafer fabs out to a 450 mm fab in 2012.
Material costs 300 mm wafer costs are higher than previous wafer size costs on both a per-wafer cost and a cost-per-square-inch basis (Fig. 5). The reason that 300 mm wafers are more expensive on a cost-per-square-inch basis is because of the higher levels of waste silicon that result from 300 mm wafer growth and the overall difficulty of growing such large wafers that meet the exacting standards of state-of-the-art IC fabrication. We are forecasting that 450 mm wafers will have a similar and in fact more severe problem.
5. 300 mm wafer costs are higher than previous wafer size costs, and 450 mm wafers are expected to have a similar and more severe problem.
Wafer and die cost projections The forecasts discussed in the preceding sections combined with additional factors not discussed here lead us to forecast wafer and die costs. For 22 nm linewidths produced on 300 mm wafers in 2012, we forecast a wafer cost of ~$9000, resulting in a quadruple-core Pentium 4t die cost of ~$16. For 22 nm linewidths produced on 450 mm wafers in 2012, we forecast a wafer cost of ~$13,000, resulting in a quadruple-core Pentium 4t die cost of ~$10. Conclusions Even with the well documented difficulties presented by the transition to 300 mm wafers, at IC Knowledge we believe the transition to 450 mm wafers will ultimately hinge on the relative cost of die produced on 450 mm wafers vs. 300 mm wafers. Based on modeling we have performed using the IC Knowledge 2005 IC Cost Model and the assumption discussed above, we believe that die costs on 450 mm wafers in the 2012 time frame will be lower than the cost of a similar die produced on 300 mm wafers. Our conclusion is that, ultimately, 450 mm wafer fabs will one day be built. References SICAS Statistics report 4th Quarter 2004. 300 mm Watch database, IC Knowledge (2005). 2005 IC Cost Model revision 0503 unreleased, IC Knowledge (2005).
Author Information
Scotten W. Jones is president of IC Knowledge LLC. He has more than 24 years of experience in the semiconductor industry, beginning his career in process engineering and working his way up to co-general manager of a semiconductor division. He has designed, built and run wafer fabs. He is also a principle in the Portsmouth Group, a senior member of IEEE, and a member of the Electrochemical Society.

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